VLSI Implementation of a Cost-Efficient 3-Lead Lossless ECG Compressor and Decompressor

Yuan Ho Chen*, Yun Hua Tseng, Pao Hsien Chu, Yen Juan, Shun Ping Wang

*Corresponding author for this work

Research output: Contribution to journalJournal Article peer-review

3 Scopus citations

Abstract

Electrocardiogram monitoring is crucial for the prevention and treatment of cardiovascular diseases. To record the electrical activity of different regions of the heart and manage the signals generated for long-term monitoring, a compression algorithm is necessary. This letter presents a novel compressor and decompressor able to support 3-lead compression without increasing hardware costs and area. The experimental results demonstrated that the bit compression ratio and power consumption can be improved by the proposed architecture. The effectiveness of this approach was verified by fabricating a chip using 0.18-μ m complementary metal-oxide-semiconductor technology. The proposed encoder has an operating frequency of 20 MHz and a gate count of 4.8K, and the proposed decoder has an operating frequency of 10 MHz and a gate count of 4.8K.

Original languageEnglish
Pages (from-to)1665-1671
Number of pages7
JournalCircuits, Systems, and Signal Processing
Volume39
Issue number3
DOIs
StatePublished - 01 03 2020

Bibliographical note

Publisher Copyright:
© 2019, Springer Science+Business Media, LLC, part of Springer Nature.

Keywords

  • Cost efficiency
  • Electrocardiography (ECG) compression algorithm
  • Multi-lead Compression
  • VLSI

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