VLSI implementation of the motion estimator with two-dimensional data-reuse

Yeong Kang Lai; Yeong Lin Lai; Yuan Chen Liu; Liang Gee Chen

doi:10.1109/30.713173

VLSI implementation of the motion estimator with two-dimensional data-reuse

Yeong Kang Lai
, Yeong Lin Lai
, Yuan Chen Liu
, Liang Gee Chen

Unknown

Research output: Contribution to journal › Journal Article › peer-review

5 Scopus citations

Abstract

This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

Original language	English
Pages (from-to)	623-629
Number of pages	7
Journal	IEEE Transactions on Consumer Electronics
Volume	44
Issue number	3
DOIs	https://doi.org/10.1109/30.713173
State	Published - 1998
Externally published	Yes

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10.1109/30.713173

Cite this

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title = "VLSI implementation of the motion estimator with two-dimensional data-reuse",

abstract = "This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100\% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.",

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N2 - This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

AB - This paper describes the VLSI implementation with two-dimensional (2-D) data-reuse architecture for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed VLSI architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

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VLSI implementation of the motion estimator with two-dimensional data-reuse

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