VLSI implementation of visual block pattern truncation coding

Yuan Chen Liu; Yeong Kang Lai; Tsung Han Tsai; Po Cheng Wu; Liang Gee Chen

doi:10.1109/30.713156

VLSI implementation of visual block pattern truncation coding

Yuan Chen Liu^*, Yeong Kang Lai, Tsung Han Tsai, Po Cheng Wu, Liang Gee Chen

^*Corresponding author for this work

Research output: Contribution to journal › Journal Article › peer-review

1 Scopus citations

Abstract

The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.

Original language	English
Pages (from-to)	490-499
Number of pages	10
Journal	IEEE Transactions on Consumer Electronics
Volume	44
Issue number	3
DOIs	https://doi.org/10.1109/30.713156
State	Published - 1998
Externally published	Yes

Keywords

Block truncation coding
VLSI implementation
Visual block pattern truncation coding
Visual pattern image coding

Access to Document

10.1109/30.713156

Cite this

@article{fcb0a787055147feb84cf8b4f7a091fd,

title = "VLSI implementation of visual block pattern truncation coding",

abstract = "The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.",

keywords = "Block truncation coding, VLSI implementation, Visual block pattern truncation coding, Visual pattern image coding",

author = "Liu, {Yuan Chen} and Lai, {Yeong Kang} and Tsai, {Tsung Han} and Wu, {Po Cheng} and Chen, {Liang Gee}",

year = "1998",

doi = "10.1109/30.713156",

language = "英语",

volume = "44",

pages = "490--499",

journal = "IEEE Transactions on Consumer Electronics",

issn = "0098-3063",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - VLSI implementation of visual block pattern truncation coding

AU - Liu, Yuan Chen

AU - Lai, Yeong Kang

AU - Tsai, Tsung Han

AU - Wu, Po Cheng

AU - Chen, Liang Gee

PY - 1998

Y1 - 1998

N2 - The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.

AB - The paper proposes a pipelined architecture of visual block pattern truncation coding algorithm to minimize mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for the moving pictures.

KW - Block truncation coding

KW - VLSI implementation

KW - Visual block pattern truncation coding

KW - Visual pattern image coding

UR - http://www.scopus.com/inward/record.url?scp=0032135936&partnerID=8YFLogxK

U2 - 10.1109/30.713156

DO - 10.1109/30.713156

M3 - 文章

AN - SCOPUS:0032135936

SN - 0098-3063

VL - 44

SP - 490

EP - 499

JO - IEEE Transactions on Consumer Electronics

JF - IEEE Transactions on Consumer Electronics

IS - 3

ER -

VLSI implementation of visual block pattern truncation coding

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this