Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis

Ken Chau Cheung Cheng; Katherine Shu-Min Li; Andrew Yi Ann Huang; Ji Wei Li; Leon Li Yang Chen; Nova Cheng-Yen Tsai; Sying Jyan Wang; Chen Shiun Lee; Leon Chou; Peter Yi Yu Liao; Hsing Chung Liang; Jwu E. Chen

doi:10.23919/DATE48585.2020.9116546

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis

Ken Chau Cheung Cheng, Katherine Shu-Min Li, Andrew Yi Ann Huang, Ji Wei Li, Leon Li Yang Chen, Nova Cheng-Yen Tsai, Sying Jyan Wang, Chen Shiun Lee, Leon Chou, Peter Yi Yu Liao, Hsing Chung Liang, Jwu E. Chen

NXP Semiconductors

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

Original language	English
Title of host publication	Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
Editors	Giorgio Di Natale, Cristiana Bolchini, Elena-Ioana Vatajelu
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1710-1711
Number of pages	2
ISBN (Electronic)	9783981926347
DOIs	https://doi.org/10.23919/DATE48585.2020.9116546
State	Published - 03 2020
Externally published	Yes
Event	2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 - Grenoble, France Duration: 09 03 2020 → 13 03 2020

Publication series

Name	Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

Conference

Conference	2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020
Country/Territory	France
City	Grenoble
Period	09/03/20 → 13/03/20

Bibliographical note

Publisher Copyright:
© 2020 EDAA.

Keywords

test path recognition
test yield
test-induced defects
wafer defect map
wafer test

Access to Document

10.23919/DATE48585.2020.9116546

Cite this

Cheng, K. C. C., Shu-Min Li, K., Huang, A. Y. A., Li, J. W., Chen, L. L. Y., Cheng-Yen Tsai, N., Wang, S. J., Lee, C. S., Chou, L., Liao, P. Y. Y., Liang, H. C., & Chen, J. E. (2020). Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. In G. Di Natale, C. Bolchini, & E.-I. Vatajelu (Eds.), Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 (pp. 1710-1711). Article 9116546 (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/DATE48585.2020.9116546

Cheng, Ken Chau Cheung ; Shu-Min Li, Katherine ; Huang, Andrew Yi Ann et al. / Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. editor / Giorgio Di Natale ; Cristiana Bolchini ; Elena-Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 1710-1711 (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

@inproceedings{53ee30a3339c474eb23d15677b327bd5,

title = "Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis",

abstract = "Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.",

keywords = "test path recognition, test yield, test-induced defects, wafer defect map, wafer test",

author = "Cheng, {Ken Chau Cheung} and {Shu-Min Li}, Katherine and Huang, {Andrew Yi Ann} and Li, {Ji Wei} and Chen, {Leon Li Yang} and {Cheng-Yen Tsai}, Nova and Wang, {Sying Jyan} and Lee, {Chen Shiun} and Leon Chou and Liao, {Peter Yi Yu} and Liang, {Hsing Chung} and Chen, {Jwu E.}",

note = "Publisher Copyright: {\textcopyright} 2020 EDAA.; 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020 ; Conference date: 09-03-2020 Through 13-03-2020",

year = "2020",

month = mar,

doi = "10.23919/DATE48585.2020.9116546",

language = "英语",

series = "Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1710--1711",

editor = "{Di Natale}, Giorgio and Cristiana Bolchini and Elena-Ioana Vatajelu",

booktitle = "Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020",

address = "美国",

}

Cheng, KCC, Shu-Min Li, K, Huang, AYA, Li, JW, Chen, LLY, Cheng-Yen Tsai, N, Wang, SJ, Lee, CS, Chou, L, Liao, PYY, Liang, HC & Chen, JE 2020, Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. in G Di Natale, C Bolchini & E-I Vatajelu (eds), Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020., 9116546, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, Institute of Electrical and Electronics Engineers Inc., pp. 1710-1711, 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, Grenoble, France, 09/03/20. https://doi.org/10.23919/DATE48585.2020.9116546

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. / Cheng, Ken Chau Cheung; Shu-Min Li, Katherine; Huang, Andrew Yi Ann et al.
Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. ed. / Giorgio Di Natale; Cristiana Bolchini; Elena-Ioana Vatajelu. Institute of Electrical and Electronics Engineers Inc., 2020. p. 1710-1711 9116546 (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis

AU - Cheng, Ken Chau Cheung

AU - Shu-Min Li, Katherine

AU - Huang, Andrew Yi Ann

AU - Li, Ji Wei

AU - Chen, Leon Li Yang

AU - Cheng-Yen Tsai, Nova

AU - Wang, Sying Jyan

AU - Lee, Chen Shiun

AU - Chou, Leon

AU - Liao, Peter Yi Yu

AU - Liang, Hsing Chung

AU - Chen, Jwu E.

PY - 2020/3

Y1 - 2020/3

N2 - Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

AB - Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

KW - test path recognition

KW - test yield

KW - test-induced defects

KW - wafer defect map

KW - wafer test

UR - http://www.scopus.com/inward/record.url?scp=85087405340&partnerID=8YFLogxK

U2 - 10.23919/DATE48585.2020.9116546

DO - 10.23919/DATE48585.2020.9116546

M3 - 会议稿件

AN - SCOPUS:85087405340

T3 - Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

SP - 1710

EP - 1711

BT - Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

A2 - Di Natale, Giorgio

A2 - Bolchini, Cristiana

A2 - Vatajelu, Elena-Ioana

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020

Y2 - 9 March 2020 through 13 March 2020

ER -

Cheng KCC, Shu-Min Li K, Huang AYA, Li JW, Chen LLY, Cheng-Yen Tsai N et al. Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. In Di Natale G, Bolchini C, Vatajelu EI, editors, Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 1710-1711. 9116546. (Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020). doi: 10.23919/DATE48585.2020.9116546

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this