Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes

P. S. Huang; M. Y. Tsai; C. Y. Huang; P. C. Lin; Lawrence Huang; Michael Chang; Steven Shih; J. P. Lin

doi:10.1109/EMAP.2012.6507849

Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes

P. S. Huang
, M. Y. Tsai^*
, C. Y. Huang
, P. C. Lin
, Lawrence Huang
, Michael Chang
, Steven Shih
, J. P. Lin

^*Corresponding author for this work

Department of Mechanical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The objective of this paper is to measure and simulate the warpage of 3D TSV (through-silicon via) die-stacked DRAM (dynamic random access memory) packages subject to thermal loading (from the room temperature to 260°C, solder reflow temperature) during manufacturing processes. The related die stresses and keep-out zone (KOZ) for the dies in the packages at the room temperature are further calculated with this validated simulation model. In the experiments, a full-field shadow moiré is used to measure the out-of-plane deformation (warpage) of packages under thermal heating conditions. A finite-element method (FEM) is applied for analyzing the thermally-induced deformation, stresses and KOZs in the packages to gain insight into their mechanics. The full-field warpages of the packages from the shadow moiré have been documented under temperature loading and compared well with FEM results. The stresses and KOZs at the proximity of a single TSV for each die in the package at the room temperature have been calculated with validated FEM model. It is found that the sizes of KOZs in four-die stacked DRAM package at the room temperature are dominated by the horizontal pMOS device and are almost double as large as the size in wafer-level die. And the sizes of KOZs are pretty much similar for each die in this four-die stacked DRAM package, even through the stresses at each die are apparently different.

Original language	English
Title of host publication	14th International Conference on Electronic Materials and Packaging, EMAP 2012
DOIs	https://doi.org/10.1109/EMAP.2012.6507849
State	Published - 2012
Event	14th International Conference on Electronic Materials and Packaging, EMAP 2012 - Lantau Island, Hong Kong Duration: 13 12 2012 → 16 12 2012

Publication series

Name	14th International Conference on Electronic Materials and Packaging, EMAP 2012

Conference

Conference	14th International Conference on Electronic Materials and Packaging, EMAP 2012
Country/Territory	Hong Kong
City	Lantau Island
Period	13/12/12 → 16/12/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

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10.1109/EMAP.2012.6507849

Cite this

Huang, P. S., Tsai, M. Y., Huang, C. Y., Lin, P. C., Huang, L., Chang, M., Shih, S., & Lin, J. P. (2012). Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes. In 14th International Conference on Electronic Materials and Packaging, EMAP 2012 Article 6507849 (14th International Conference on Electronic Materials and Packaging, EMAP 2012). https://doi.org/10.1109/EMAP.2012.6507849

@inproceedings{ba5a02ecfe74445c85dd3bfb00724bc0,

title = "Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes",

abstract = "The objective of this paper is to measure and simulate the warpage of 3D TSV (through-silicon via) die-stacked DRAM (dynamic random access memory) packages subject to thermal loading (from the room temperature to 260°C, solder reflow temperature) during manufacturing processes. The related die stresses and keep-out zone (KOZ) for the dies in the packages at the room temperature are further calculated with this validated simulation model. In the experiments, a full-field shadow moir{\'e} is used to measure the out-of-plane deformation (warpage) of packages under thermal heating conditions. A finite-element method (FEM) is applied for analyzing the thermally-induced deformation, stresses and KOZs in the packages to gain insight into their mechanics. The full-field warpages of the packages from the shadow moir{\'e} have been documented under temperature loading and compared well with FEM results. The stresses and KOZs at the proximity of a single TSV for each die in the package at the room temperature have been calculated with validated FEM model. It is found that the sizes of KOZs in four-die stacked DRAM package at the room temperature are dominated by the horizontal pMOS device and are almost double as large as the size in wafer-level die. And the sizes of KOZs are pretty much similar for each die in this four-die stacked DRAM package, even through the stresses at each die are apparently different.",

author = "Huang, \{P. S.\} and Tsai, \{M. Y.\} and Huang, \{C. Y.\} and Lin, \{P. C.\} and Lawrence Huang and Michael Chang and Steven Shih and Lin, \{J. P.\}",

year = "2012",

doi = "10.1109/EMAP.2012.6507849",

language = "英语",

isbn = "9781467349444",

series = "14th International Conference on Electronic Materials and Packaging, EMAP 2012",

booktitle = "14th International Conference on Electronic Materials and Packaging, EMAP 2012",

note = "14th International Conference on Electronic Materials and Packaging, EMAP 2012 ; Conference date: 13-12-2012 Through 16-12-2012",

}

Huang, PS, Tsai, MY, Huang, CY, Lin, PC, Huang, L, Chang, M, Shih, S & Lin, JP 2012, Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes. in 14th International Conference on Electronic Materials and Packaging, EMAP 2012., 6507849, 14th International Conference on Electronic Materials and Packaging, EMAP 2012, 14th International Conference on Electronic Materials and Packaging, EMAP 2012, Lantau Island, Hong Kong, 13/12/12. https://doi.org/10.1109/EMAP.2012.6507849

Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes. / Huang, P. S.; Tsai, M. Y.; Huang, C. Y. et al.
14th International Conference on Electronic Materials and Packaging, EMAP 2012. 2012. 6507849 (14th International Conference on Electronic Materials and Packaging, EMAP 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes

AU - Huang, P. S.

AU - Tsai, M. Y.

AU - Huang, C. Y.

AU - Lin, P. C.

AU - Huang, Lawrence

AU - Chang, Michael

AU - Shih, Steven

AU - Lin, J. P.

PY - 2012

Y1 - 2012

N2 - The objective of this paper is to measure and simulate the warpage of 3D TSV (through-silicon via) die-stacked DRAM (dynamic random access memory) packages subject to thermal loading (from the room temperature to 260°C, solder reflow temperature) during manufacturing processes. The related die stresses and keep-out zone (KOZ) for the dies in the packages at the room temperature are further calculated with this validated simulation model. In the experiments, a full-field shadow moiré is used to measure the out-of-plane deformation (warpage) of packages under thermal heating conditions. A finite-element method (FEM) is applied for analyzing the thermally-induced deformation, stresses and KOZs in the packages to gain insight into their mechanics. The full-field warpages of the packages from the shadow moiré have been documented under temperature loading and compared well with FEM results. The stresses and KOZs at the proximity of a single TSV for each die in the package at the room temperature have been calculated with validated FEM model. It is found that the sizes of KOZs in four-die stacked DRAM package at the room temperature are dominated by the horizontal pMOS device and are almost double as large as the size in wafer-level die. And the sizes of KOZs are pretty much similar for each die in this four-die stacked DRAM package, even through the stresses at each die are apparently different.

AB - The objective of this paper is to measure and simulate the warpage of 3D TSV (through-silicon via) die-stacked DRAM (dynamic random access memory) packages subject to thermal loading (from the room temperature to 260°C, solder reflow temperature) during manufacturing processes. The related die stresses and keep-out zone (KOZ) for the dies in the packages at the room temperature are further calculated with this validated simulation model. In the experiments, a full-field shadow moiré is used to measure the out-of-plane deformation (warpage) of packages under thermal heating conditions. A finite-element method (FEM) is applied for analyzing the thermally-induced deformation, stresses and KOZs in the packages to gain insight into their mechanics. The full-field warpages of the packages from the shadow moiré have been documented under temperature loading and compared well with FEM results. The stresses and KOZs at the proximity of a single TSV for each die in the package at the room temperature have been calculated with validated FEM model. It is found that the sizes of KOZs in four-die stacked DRAM package at the room temperature are dominated by the horizontal pMOS device and are almost double as large as the size in wafer-level die. And the sizes of KOZs are pretty much similar for each die in this four-die stacked DRAM package, even through the stresses at each die are apparently different.

UR - https://www.scopus.com/pages/publications/84880279122

U2 - 10.1109/EMAP.2012.6507849

DO - 10.1109/EMAP.2012.6507849

M3 - 会议稿件

AN - SCOPUS:84880279122

SN - 9781467349444

T3 - 14th International Conference on Electronic Materials and Packaging, EMAP 2012

BT - 14th International Conference on Electronic Materials and Packaging, EMAP 2012

T2 - 14th International Conference on Electronic Materials and Packaging, EMAP 2012

Y2 - 13 December 2012 through 16 December 2012

ER -

Warpage, stresses and KOZ of 3D TSV DRAM package during manufacturing processes

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