YOR: A Yield-Optimizing Routing Algorithm by Minimizing Critical Areas and Vias

The goal of a channel routing algorithm is to route all the nets with as few tracks as possible to minimize chip areas and achieve 100% connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce critical areas which are susceptible to defects. These critical areas are caused by the highly compacted adjacent wires and vias in the routing region. A new channel routing algorithm, the yield optimizing routing (YOR) algorithm, is presented in this paper to deal with this problem. Our approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The YOR algorithm also minimizes the number of vias since vias in a chip will increase manufacturing complexity and hence degrade the yield. YOR has been implemented and applied to benchmark routing layouts in the literature. Experimental results show that large reduction in the number of critical areas and significant improvement in yield are achieved, particularly for practical size channels such as Deutsch’s difficult problem.