抗軟錯誤之栓鎖器/暫存器電路設計與晶片實現

Engineering

1. Flip Flop Circuits 100%
2. Circuit Design 100%
3. Single Event Upset 100%
4. Soft Error 100%
5. System-on-Chip 59%
6. Error Rate 47%
7. Transistor 17%
8. Supply Voltage 11%
9. Output Node 11%
10. Contention 11%
11. Feedback Path 11%
12. Clock Signal 11%
13. Schmitt Trigger 11%
14. Fits and Tolerances 11%
15. Noise Immunity 11%
16. Gate Capacitance 11%
17. Nanoscale 11%
18. Design Complexity 11%
19. Propagation Delay 11%
20. Power Supply Voltage 11%

Computer Science

1. Soft Error 100%
2. System-on-Chip 71%
3. Transistor 21%
4. Control Signal 14%
5. Propagation Delay 14%
6. Design Challenge 14%
7. Design Complexity 14%
8. Gate Capacitance 14%