A 0.5V high speed DRAM charge transfer sense amplifier

Hwang Cherng Chow*, Chaung Lin Hsieh

*此作品的通信作者

研究成果: 圖書/報告稿件的類型會議稿件同行評審

4 引文 斯高帕斯(Scopus)

摘要

A new charge transfer sense amplifier scheme is proposed for high speed 0.5V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.

原文英語
主出版物標題2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference Proceedings
頁面1293-1296
頁數4
DOIs
出版狀態已出版 - 2007
事件2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference - Montreal, QC, 加拿大
持續時間: 05 08 200708 08 2007

出版系列

名字Midwest Symposium on Circuits and Systems
ISSN(列印)1548-3746

Conference

Conference2007 50th Midwest Symposium on Circuits and Systems, MWSCAS - Conference
國家/地區加拿大
城市Montreal, QC
期間05/08/0708/08/07

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