A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT

Fan Hsiu Huang; Cheng Kuo Lin; Yu Chi Wang; Yi Jen Chan

doi:10.1109/CSICS07.2007.43

A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT

Fan Hsiu Huang^*, Cheng Kuo Lin, Yu Chi Wang, Yi Jen Chan

^*此作品的通信作者

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A phase-locked loop (PLL) MMIC based on a ring-type injection-locked frequency divider (RILFD) and a cascode-type voltage-controlled oscillator (VCO) has been manufactured by using 0.5 μm enhanced/depletion mode (E/D) GaAs pHEMTs for Ka-band communications. In this circuit, the 15 GHz cascode oscillator including the 2^nd harmonic cascode buffer amplifier was designed to generate a 30 GHz output signal. To synchronize the oscillation signal with the input reference signal, the wide locking-range divided-by-four RILFD using injection-locked technique and the cascode mixer to be a phase detector were used with a reference signal of 3.75 GHz. With a RC low-pass filter and a dc amplifier based on the E/D-mode inverter circuit, the loop gain and the output phase noise can be further improved. The measured result of the locking range is about 400 MHz near 30 GHz and the output phase noise is about -116 dBc/Hz at 1 MHz offset under a 2 V dc supply with 80 mW power consumption.

原文	英語
主出版物標題	29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium
主出版物子標題	"Tastes of the Northwest" - Technical Digest 2007
頁面	158-161
頁數	4
DOIs	https://doi.org/10.1109/CSICS07.2007.43
出版狀態	已出版 - 2007
對外發佈	是
事件	29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest" - Portland, OR, 美國持續時間: 14 10 2007 → 17 10 2007

出版系列

名字	Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
ISSN（列印）	1550-8781

Conference

Conference	29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest"
國家/地區	美國
城市	Portland, OR
期間	14/10/07 → 17/10/07

存取文件

10.1109/CSICS07.2007.43

其它文件與鏈接

Link to publication in Scopus

引用此

Huang, F. H., Lin, C. K., Wang, Y. C., & Chan, Y. J. (2007). A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT. 於 29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest" - Technical Digest 2007 (頁 158-161). 文章 4384423 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). https://doi.org/10.1109/CSICS07.2007.43

Huang, Fan Hsiu ; Lin, Cheng Kuo ; Wang, Yu Chi 等. / A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT. 29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest" - Technical Digest 2007. 2007. 頁 158-161 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC).

@inproceedings{e091d42d6b6743f0939c49a54e01fddd,

title = "A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT",

abstract = "A phase-locked loop (PLL) MMIC based on a ring-type injection-locked frequency divider (RILFD) and a cascode-type voltage-controlled oscillator (VCO) has been manufactured by using 0.5 μm enhanced/depletion mode (E/D) GaAs pHEMTs for Ka-band communications. In this circuit, the 15 GHz cascode oscillator including the 2nd harmonic cascode buffer amplifier was designed to generate a 30 GHz output signal. To synchronize the oscillation signal with the input reference signal, the wide locking-range divided-by-four RILFD using injection-locked technique and the cascode mixer to be a phase detector were used with a reference signal of 3.75 GHz. With a RC low-pass filter and a dc amplifier based on the E/D-mode inverter circuit, the loop gain and the output phase noise can be further improved. The measured result of the locking range is about 400 MHz near 30 GHz and the output phase noise is about -116 dBc/Hz at 1 MHz offset under a 2 V dc supply with 80 mW power consumption.",

keywords = "Cascode circuit topology, Enhanced/depletion mode GaAs pHEMTs, Phase-locked loop",

author = "Huang, {Fan Hsiu} and Lin, {Cheng Kuo} and Wang, {Yu Chi} and Chan, {Yi Jen}",

year = "2007",

doi = "10.1109/CSICS07.2007.43",

language = "英语",

isbn = "1424410223",

series = "Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC",

pages = "158--161",

booktitle = "29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium",

note = "29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: {"}Tastes of the Northwest{"} ; Conference date: 14-10-2007 Through 17-10-2007",

}

Huang, FH, Lin, CK, Wang, YC & Chan, YJ 2007, A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT. 於 29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest" - Technical Digest 2007., 4384423, Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC, 頁 158-161, 29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest", Portland, OR, 美國, 14/10/07. https://doi.org/10.1109/CSICS07.2007.43

A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT. / Huang, Fan Hsiu; Lin, Cheng Kuo; Wang, Yu Chi 等.
29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest" - Technical Digest 2007. 2007. p. 158-161 4384423 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT

AU - Huang, Fan Hsiu

AU - Lin, Cheng Kuo

AU - Wang, Yu Chi

AU - Chan, Yi Jen

PY - 2007

Y1 - 2007

N2 - A phase-locked loop (PLL) MMIC based on a ring-type injection-locked frequency divider (RILFD) and a cascode-type voltage-controlled oscillator (VCO) has been manufactured by using 0.5 μm enhanced/depletion mode (E/D) GaAs pHEMTs for Ka-band communications. In this circuit, the 15 GHz cascode oscillator including the 2nd harmonic cascode buffer amplifier was designed to generate a 30 GHz output signal. To synchronize the oscillation signal with the input reference signal, the wide locking-range divided-by-four RILFD using injection-locked technique and the cascode mixer to be a phase detector were used with a reference signal of 3.75 GHz. With a RC low-pass filter and a dc amplifier based on the E/D-mode inverter circuit, the loop gain and the output phase noise can be further improved. The measured result of the locking range is about 400 MHz near 30 GHz and the output phase noise is about -116 dBc/Hz at 1 MHz offset under a 2 V dc supply with 80 mW power consumption.

AB - A phase-locked loop (PLL) MMIC based on a ring-type injection-locked frequency divider (RILFD) and a cascode-type voltage-controlled oscillator (VCO) has been manufactured by using 0.5 μm enhanced/depletion mode (E/D) GaAs pHEMTs for Ka-band communications. In this circuit, the 15 GHz cascode oscillator including the 2nd harmonic cascode buffer amplifier was designed to generate a 30 GHz output signal. To synchronize the oscillation signal with the input reference signal, the wide locking-range divided-by-four RILFD using injection-locked technique and the cascode mixer to be a phase detector were used with a reference signal of 3.75 GHz. With a RC low-pass filter and a dc amplifier based on the E/D-mode inverter circuit, the loop gain and the output phase noise can be further improved. The measured result of the locking range is about 400 MHz near 30 GHz and the output phase noise is about -116 dBc/Hz at 1 MHz offset under a 2 V dc supply with 80 mW power consumption.

KW - Cascode circuit topology

KW - Enhanced/depletion mode GaAs pHEMTs

KW - Phase-locked loop

UR - http://www.scopus.com/inward/record.url?scp=47349121351&partnerID=8YFLogxK

U2 - 10.1109/CSICS07.2007.43

DO - 10.1109/CSICS07.2007.43

M3 - 会议稿件

AN - SCOPUS:47349121351

SN - 1424410223

SN - 9781424410224

T3 - Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

SP - 158

EP - 161

BT - 29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium

T2 - 29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest"

Y2 - 14 October 2007 through 17 October 2007

ER -

Huang FH, Lin CK, Wang YC, Chan YJ. A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT. 於 29th Annual IEEE Compound Semiconductor Integrated Circuit Symposium 2007 IEEE CSIC Symposium: "Tastes of the Northwest" - Technical Digest 2007. 2007. p. 158-161. 4384423. (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). doi: 10.1109/CSICS07.2007.43

A 30 GHz single-chip PLL MMIC using 0.5μm enhanced/depletion-mode GaAs pHEMT

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此