TY - JOUR
T1 - A 3.3V 1GHz high speed pipelined booth multiplier
AU - Chow, Hwang Cherng
AU - Wey, I. Chyn
PY - 2002
Y1 - 2002
N2 - In this paper, a new MBE (modified Booth encoding) recoder, and a new MBE decoder are proposed in CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of critical path by levelizing the complex gate in the MBE decoder. As a result, MBE decoder is never the speed bottleneck of a pipelined booth multiplier, and the speed of the MBE decoder can be improved up to 66.3 percent. Finally, a low voltage, high speed pipelined glitch-free Booth multiplier architecture is presented at 1Ghz in TSMC 0.35um process with a power consumption of only 100.52mw.
AB - In this paper, a new MBE (modified Booth encoding) recoder, and a new MBE decoder are proposed in CMOS transistor level to improve the performance of traditional multipliers. The proposed pipelined Booth multiplier can reduce the delay time of critical path by levelizing the complex gate in the MBE decoder. As a result, MBE decoder is never the speed bottleneck of a pipelined booth multiplier, and the speed of the MBE decoder can be improved up to 66.3 percent. Finally, a low voltage, high speed pipelined glitch-free Booth multiplier architecture is presented at 1Ghz in TSMC 0.35um process with a power consumption of only 100.52mw.
UR - http://www.scopus.com/inward/record.url?scp=0036292214&partnerID=8YFLogxK
M3 - 会议文章
AN - SCOPUS:0036292214
SN - 0271-4310
VL - 1
SP - I/457-I/460
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - 2002 IEEE International Symposium on Circuits and Systems
Y2 - 26 May 2002 through 29 May 2002
ER -