TY - JOUR
T1 - A 3.3V 1GHz low-latency pipelined booth multiplier with new Manchester carry-bypass adder
AU - Cho, Hwang Cherng
AU - Wey, I. Chyn
PY - 2003
Y1 - 2003
N2 - In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above IGHz with worst-case delay of 0.833ns and consumed only 16.81mw. Finally, the proposed pipelined Booth multiplier is presented at 3.3V, IGHz in TSMC 0.35um process with a power consumption of only 60.18mw.
AB - In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above IGHz with worst-case delay of 0.833ns and consumed only 16.81mw. Finally, the proposed pipelined Booth multiplier is presented at 3.3V, IGHz in TSMC 0.35um process with a power consumption of only 60.18mw.
UR - http://www.scopus.com/inward/record.url?scp=0037744612&partnerID=8YFLogxK
M3 - 会议文章
AN - SCOPUS:0037744612
SN - 0271-4310
VL - 5
SP - V121-V124
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems
Y2 - 25 May 2003 through 28 May 2003
ER -