A 3.3V 1GHz low-latency pipelined booth multiplier with new Manchester carry-bypass adder

Hwang Cherng Cho; I. Chyn Wey

A 3.3V 1GHz low-latency pipelined booth multiplier with new Manchester carry-bypass adder

Hwang Cherng Cho^*
, I. Chyn Wey

^*此作品的通信作者

研究成果: 期刊稿件 › 會議文章 › 同行評審

7 引文斯高帕斯（Scopus）

摘要

In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above IGHz with worst-case delay of 0.833ns and consumed only 16.81mw. Finally, the proposed pipelined Booth multiplier is presented at 3.3V, IGHz in TSMC 0.35um process with a power consumption of only 60.18mw.

原文	英語
頁（從 - 到）	V121-V124
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	5
出版狀態	已出版 - 2003
事件	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, 泰國持續時間: 25 05 2003 → 28 05 2003

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title = "A 3.3V 1GHz low-latency pipelined booth multiplier with new Manchester carry-bypass adder",

abstract = "In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16\% improvement and the energy can be saved with 30.59\% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above IGHz with worst-case delay of 0.833ns and consumed only 16.81mw. Finally, the proposed pipelined Booth multiplier is presented at 3.3V, IGHz in TSMC 0.35um process with a power consumption of only 60.18mw.",

author = "Cho, \{Hwang Cherng\} and Wey, \{I. Chyn\}",

year = "2003",

language = "英语",

volume = "5",

pages = "V121--V124",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

}

TY - JOUR

T1 - A 3.3V 1GHz low-latency pipelined booth multiplier with new Manchester carry-bypass adder

AU - Cho, Hwang Cherng

AU - Wey, I. Chyn

PY - 2003

Y1 - 2003

N2 - In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above IGHz with worst-case delay of 0.833ns and consumed only 16.81mw. Finally, the proposed pipelined Booth multiplier is presented at 3.3V, IGHz in TSMC 0.35um process with a power consumption of only 60.18mw.

AB - In this paper, a high speed, low latency pipelined Booth multiplier with new Manchester carry-bypass adder (MCBA) is proposed. By using new partial product generation scheme and new MCBA, the latency is reduced to 6. By using new MCBA, the speed bottleneck is overcome with 40.16% improvement and the energy can be saved with 30.59% improvement. The 13-bit new MCBA pipelined into 2 stages can operate above IGHz with worst-case delay of 0.833ns and consumed only 16.81mw. Finally, the proposed pipelined Booth multiplier is presented at 3.3V, IGHz in TSMC 0.35um process with a power consumption of only 60.18mw.

UR - https://www.scopus.com/pages/publications/0037744612

M3 - 会议文章

AN - SCOPUS:0037744612

SN - 0271-4310

VL - 5

SP - V121-V124

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

A 3.3V 1GHz low-latency pipelined booth multiplier with new Manchester carry-bypass adder

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