A Convolutional Neural Network Inference Accelerator Design using Algorithmic Noise-Tolerance Technology

A high-performance chip for CNN inference was proposed in this work, which utilized the Algorithmic Noise-Tolerance (ANT) architecture as the core technology for modification. The error tolerance characteristics of CNN made ANT architecture a suitable choice. However, current ANT acquires a separated Residue Processing and Reduction (RPR) circuit, which is power and area-hungry. An Integrated RPR (I-RPR) approach was thus proposed to mitigate these shortcomings. The overall hardware architecture is divided into main and secondary blocks, and the appropriate operation mode is selected based on the importance of image features. RPR was integrated into the main arithmetic circuits. The original calculations are split, and RPR circuits remove redundant parts. The proposed I-RPR CNN chip was validated on the VGG16 model using the CIFAR-10 dataset. I-RPR was implemented in TSMC 90-nm CMOS technology at 0.9 V power supply and 100 MHz operating frequency. The I-RPR CNN chip achieved a power reduction of about 90%, area reduction of 45%, and more than 20% reduction in computing time with a 1.25% drop in inference accuracy.