A delay-locked loop with self-calibration circuit for reducing phase error

A delay-locked loop with self-calibration circuit for reducing phase error is presented. In this DLL, the current mismatch adjusting circuit is proposed in order to reduce the static phase error. To reduce the static phase error the circuit eliminates the mismatch of up/down currents in the charge pump (CP). The current mismatch adjusting circuit is implemented with phase expanded circuit to amplifier the static phase error. To solve the false locking problem, a new phase detector is proposed. The proposed circuit has been fabricated in a 0.18 μm CMOS process. The measured static phase errors are without and with calibration circuit are 29 ps and 3.89 ps at 1.2 GHz, respectively.