A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

Yu Che Yang; Shih An Yu; Tao Wang; Shey Shi Lu

doi:10.1109/LMWC.2005.858978

A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

Yu Che Yang^*
, Shih An Yu
, Tao Wang
, Shey Shi Lu

^*此作品的通信作者

National Taiwan University

研究成果: 期刊稿件 › 文章 › 同行評審

14 引文斯高帕斯（Scopus）

摘要

A divide-by-1/1.5 divider cell using a dual edgetrigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-μm CMOS technology, where X = P or P.5 in one mode and 2P or 2P+1 in the other mode with P = 128-255. When operated in the divide-by-IP/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.

原文	英語
頁（從 - 到）	754-756
頁數	3
期刊	IEEE Microwave and Wireless Components Letters
卷	15
發行號	11
DOIs	https://doi.org/10.1109/LMWC.2005.858978
出版狀態	已出版 - 11 2005
對外發佈	是

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title = "A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell",

abstract = "A divide-by-1/1.5 divider cell using a dual edgetrigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-μm CMOS technology, where X = P or P.5 in one mode and 2P or 2P+1 in the other mode with P = 128-255. When operated in the divide-by-IP/2P+1 mode, this circuit outputs a signal with 50\% duty cycle. Theoretically, P can be any arbitrary and programmable integer.",

keywords = "50\% duty cycle and phase-locked loop (PLL), Fractional divider, Programmable divider",

author = "Yang, \{Yu Che\} and Yu, \{Shih An\} and Tao Wang and Lu, \{Shey Shi\}",

year = "2005",

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doi = "10.1109/LMWC.2005.858978",

language = "英语",

volume = "15",

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AU - Yang, Yu Che

AU - Yu, Shih An

AU - Wang, Tao

AU - Lu, Shey Shi

PY - 2005/11

Y1 - 2005/11

N2 - A divide-by-1/1.5 divider cell using a dual edgetrigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-μm CMOS technology, where X = P or P.5 in one mode and 2P or 2P+1 in the other mode with P = 128-255. When operated in the divide-by-IP/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.

AB - A divide-by-1/1.5 divider cell using a dual edgetrigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-μm CMOS technology, where X = P or P.5 in one mode and 2P or 2P+1 in the other mode with P = 128-255. When operated in the divide-by-IP/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.

KW - 50% duty cycle and phase-locked loop (PLL)

KW - Fractional divider

KW - Programmable divider

UR - https://www.scopus.com/pages/publications/28744454779

U2 - 10.1109/LMWC.2005.858978

DO - 10.1109/LMWC.2005.858978

M3 - 文章

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SN - 1531-1309

VL - 15

SP - 754

EP - 756

JO - IEEE Microwave and Wireless Components Letters

JF - IEEE Microwave and Wireless Components Letters

IS - 11

ER -

A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

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