A fast-corrected all-digital DCC with synchronous input clock

Shao Ku Kao, Sheng Hung Hsueh*


研究成果: 期刊稿件文章同行評審

1 引文 斯高帕斯(Scopus)


This paper presents a fast-corrected all-digital duty-cycle corrector (DCC) with synchronous input clock. The proposed DCC has many features, including fast locking in 4 cycles, wide range correction, and synchronous 50% duty-cycle clock with an input clock. The circuit can operate from 500 to 900 MHz and corrects a wide range of input duty cycle ranging from 25 to 75%. The duty-cycle error of the output clock is between -2.4 and 2.7%. The largest static phase error between the input and output clock is -44 ps at 900 MHz. The RMS and peak-to-peak jitters are 1.9 and 14.7 ps at 900 MHz, respectively. The proposed DCC is implemented in a 0.18-μm complementary metal oxide semiconductor process. The proposed DCC occupies an area of 0.05 mm2 and dissipates 23 mW with 1.8-V supply voltage at 900 MHz.

頁(從 - 到)1845-1860
期刊International Journal of Circuit Theory and Applications
出版狀態已出版 - 01 12 2015


Publisher Copyright:
Copyright © 2014 John Wiley & Sons, Ltd.


深入研究「A fast-corrected all-digital DCC with synchronous input clock」主題。共同形成了獨特的指紋。