摘要
This paper presents a low drop-out (LDO) regulator with feed-forward ripple cancellation (FFRC) technique, utilizing a capacitively coupled method. Power supply rejection (PSR) is identified as one of the most critical specifications, alongside performance over a wide frequency range and at maximum load current. The paper presents a technique to enhance the PSR of the LDO and demonstrates the feasibility and relevance of these methods through equation derivation. The proposed LDO is designed using a 0.18 Âμm process, with input voltage specifications ranging from 1.3 V to 1.8 V, an output voltage of 1.2 V, and a static current consumption of 38.6 ÂμA, utilizing an external regulator capacitor of 1 ÂμF. This design achieves a PSR of -60 dB at load currents ranging from 1 mA to 40 mA. It also extends the bandwidth when the LDO is supplied with larger load currents, achieving a PSR of -73 dB at a frequency of 500 kHz and maintaining a PSR of -61 dB or more at 1 MHz.
| 原文 | 英語 |
|---|---|
| 頁(從 - 到) | 37-46 |
| 頁數 | 10 |
| 期刊 | IEEE Nanotechnology Magazine |
| 卷 | 18 |
| 發行號 | 5 |
| DOIs | |
| 出版狀態 | 已出版 - 2024 |
文獻附註
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