A new all-digital phase-locked loop with high precision and low jitter

Hwang Cherng Chow*, Chung Hsin Su

*此作品的通信作者

研究成果: 期刊稿件文章同行評審

6 引文 斯高帕斯(Scopus)

摘要

A new method is proposed in this article to accomplish the fine tune unit of the digitally controlled oscillator of an all-digital phase-locked loop (ADPLL). Instead of using adjustable currents, we utilise the difference of the equivalent capacitance obtained from the drain of MOS transistors between on and off states as the fine tune delay parameter. Based on post-layout simulation results, the time resolution of the fine tune delay element can achieve results as good as 1.7126ps. The operating frequency of this presented ADPLL ranges from 308 to 587MHz. As compared to prior arts, the power consumption per MHz is reduced over 15% and the jitter is as low as 5ps, which is a significant improvement.

原文英語
頁(從 - 到)1241-1249
頁數9
期刊International Journal of Electronics
95
發行號12
DOIs
出版狀態已出版 - 01 2008

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