A new phase-locked loop with enhanced lock-in design

In this paper, we propose a new phase-locked loop design with both a high speed phase frequency detector and an enhanced lock-in feature. The proposed phase frequency detector is simple in its circuit structure and has no glitch output. Therefore, better phase characteristics can be obtained. Based on simulation results, the proposed phase frequency detector shows satisfactory circuit performance with a very high operation frequency up to 3.5 GHz. Moreover, advantages of lower phase jitter and smaller circuit complexity are achieved as compared to prior art circuits. Furthermore, we present an auxiliary enhanced lock-in system for the phase-locked loop. The proposed mechanism can reduce the lock-time effectively over 50 percent by using the reference clock signal only. Besides, the whole enhanced lock-in circuit performs its operation in one reference clock cycle.