A quantization noise suppression technique for Δ ∑ fractional-N frequency synthesizers

The first circuit implementation of quantization noise suppression technique for Δ ∑ fractional- N frequency synthesizers using reduced step size of frequency dividers is presented in this paper. This technique is based on a 1/1.5 divider cell which can reduce the step size of the frequency divider to 0.5 and thus the reduced step size suppresses the quantization noise by 6 dB. This frequency synthesizer is intended for a WLAN 802.11a/WiMAX 802.16e transceiver. This chip is implemented in a 0.18-μm CMOS process and the die size is 1.23 mm × 0.83 mm. The power consumption is 47.8 mW. The in-band phase noise of - 100 dBc/Hz at 10 kHz offset and out-of-band phase noise of - 124 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The frequency resolution is less than 1 Hz and the lock time is smaller than 10 μs.