A real-time FPGA based human detector

Pei Yung Hsiao, Shih Yu Lin, Chuen Yau Chen

研究成果: 圖書/報告稿件的類型會議稿件同行評審

14 引文 斯高帕斯(Scopus)

摘要

An ARM-platform and FPGA-based accelerator rather than PC-based system is utilized in this study for completing a real-time FPGA-based human detector. The system presents the advantages of small size, low cost, high computing speed, and being portable and could be built in small cameras for surveillance applications. When background segmentation is introduced, the computing efficiency could reach about 15 fps. Moreover, this study has proven that the reduction on the total detection rate is less than 0.3% while changing HOG algorithm into the presented FPGA hardware implementation.

原文英語
主出版物標題Proceedings - 2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016
發行者Institute of Electrical and Electronics Engineers Inc.
頁面1014-1017
頁數4
ISBN(電子)9781509030712
DOIs
出版狀態已出版 - 16 08 2016
對外發佈
事件2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016 - Xi'an, 中國
持續時間: 04 07 201606 07 2016

出版系列

名字Proceedings - 2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016

Conference

Conference2016 IEEE International Symposium on Computer, Consumer and Control, IS3C 2016
國家/地區中國
城市Xi'an
期間04/07/1606/07/16

文獻附註

Publisher Copyright:
© 2016 IEEE.

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