A Temporal Assertion Extension to Verilog

Kai Hui Chang; Wei Ting Tu; Yi Jong Yeh; Sy Yen Kuo

doi:10.1007/978-3-540-30476-0_45

A Temporal Assertion Extension to Verilog

Kai Hui Chang^*
, Wei Ting Tu
, Yi Jong Yeh
, Sy Yen Kuo

^*此作品的通信作者

National Taiwan University

研究成果: 圖書/報告稿件的類型 › 章節 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.

原文	英語
主出版物標題	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
編輯	Farn Wang
發行者	Springer Verlag
頁面	499-504
頁數	6
ISBN（列印）	9783540236108
DOIs	https://doi.org/10.1007/978-3-540-30476-0_45
出版狀態	已出版 - 2004
對外發佈	是

出版系列

名字	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
卷	3299
ISSN（列印）	0302-9743
ISSN（電子）	1611-3349

存取文件

10.1007/978-3-540-30476-0_45

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Link to publication in Scopus

引用此

Chang, K. H., Tu, W. T., Yeh, Y. J., & Kuo, S. Y. (2004). A Temporal Assertion Extension to Verilog. 於 F. Wang (編輯), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (頁 499-504). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 3299). Springer Verlag. https://doi.org/10.1007/978-3-540-30476-0_45

Chang, Kai Hui ; Tu, Wei Ting ; Yeh, Yi Jong 等. / A Temporal Assertion Extension to Verilog. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 編輯 / Farn Wang. Springer Verlag, 2004. 頁 499-504 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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abstract = "Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.",

keywords = "PSL, Temporal assertion, Verification",

author = "Chang, \{Kai Hui\} and Tu, \{Wei Ting\} and Yeh, \{Yi Jong\} and Kuo, \{Sy Yen\}",

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Chang, KH, Tu, WT, Yeh, YJ & Kuo, SY 2004, A Temporal Assertion Extension to Verilog. 於 F Wang (編輯), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 卷 3299, Springer Verlag, 頁 499-504. https://doi.org/10.1007/978-3-540-30476-0_45

A Temporal Assertion Extension to Verilog. / Chang, Kai Hui; Tu, Wei Ting; Yeh, Yi Jong 等.
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 編輯 / Farn Wang. Springer Verlag, 2004. p. 499-504 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 卷 3299).

研究成果: 圖書/報告稿件的類型 › 章節 › 同行評審

TY - CHAP

T1 - A Temporal Assertion Extension to Verilog

AU - Chang, Kai Hui

AU - Tu, Wei Ting

AU - Yeh, Yi Jong

AU - Kuo, Sy Yen

PY - 2004

Y1 - 2004

N2 - Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.

AB - Many circuit designs need to follow some temporal rules. However, it is hard to express and verify them in the past. Therefore, a temporal assertion extension to Verilog, called Temporal Wizard, is proposed in this paper. It provides several Verilog system tasks for the users to write assertions in testbench directly. Two new concepts, tag and thread, are also introduced so that data can be associated with temporal assertions and provide more functionalities than previous temporal assertion checkers.

KW - PSL

KW - Temporal assertion

KW - Verification

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M3 - 章节

AN - SCOPUS:26844565409

SN - 9783540236108

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

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BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

A2 - Wang, Farn

PB - Springer Verlag

ER -

Chang KH, Tu WT, Yeh YJ, Kuo SY. A Temporal Assertion Extension to Verilog. 於 Wang F, 編輯, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Springer Verlag. 2004. p. 499-504. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/978-3-540-30476-0_45

A Temporal Assertion Extension to Verilog

摘要

出版系列

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引用此