An analog neural network processor for self-organizing mapping

Bing J. Sheu; Joongho Choi; Chia Fen Chang

doi:10.1109/ISSCC.1992.200449

An analog neural network processor for self-organizing mapping

Bing J. Sheu, Joongho Choi, Chia Fen Chang

University of Southern California

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

10 引文斯高帕斯（Scopus）

摘要

The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.

原文	英語
主出版物標題	Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	136-137
頁數	2
ISBN（電子）	0780305736
DOIs	https://doi.org/10.1109/ISSCC.1992.200449
出版狀態	已出版 - 1992
對外發佈	是
事件	39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, 美國持續時間: 19 02 1992 → 21 02 1992

出版系列

名字	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
卷	1992-February
ISSN（列印）	0193-6530

Conference

Conference	39th IEEE International Solid-State Circuits Conference, ISSCC 1992
國家/地區	美國
城市	San Francisco
期間	19/02/92 → 21/02/92

文獻附註

Publisher Copyright:
© 1992 IEEE.

存取文件

10.1109/ISSCC.1992.200449

其它文件與鏈接

Link to publication in Scopus

引用此

Sheu, B. J., Choi, J., & Chang, C. F. (1992). An analog neural network processor for self-organizing mapping. 於 Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 (頁 136-137). 文章 200449 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 1992-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.1992.200449

Sheu, Bing J. ; Choi, Joongho ; Chang, Chia Fen. / An analog neural network processor for self-organizing mapping. Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. 頁 136-137 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{14832f6d675f40a6bfc0aac2db283c56,

title = "An analog neural network processor for self-organizing mapping",

abstract = "The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.",

author = "Sheu, {Bing J.} and Joongho Choi and Chang, {Chia Fen}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 39th IEEE International Solid-State Circuits Conference, ISSCC 1992 ; Conference date: 19-02-1992 Through 21-02-1992",

year = "1992",

doi = "10.1109/ISSCC.1992.200449",

language = "英语",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "136--137",

booktitle = "Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992",

address = "美国",

}

Sheu, BJ, Choi, J & Chang, CF 1992, An analog neural network processor for self-organizing mapping. 於 Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992., 200449, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 卷 1992-February, Institute of Electrical and Electronics Engineers Inc., 頁 136-137, 39th IEEE International Solid-State Circuits Conference, ISSCC 1992, San Francisco, 美國, 19/02/92. https://doi.org/10.1109/ISSCC.1992.200449

An analog neural network processor for self-organizing mapping. / Sheu, Bing J.; Choi, Joongho; Chang, Chia Fen.
Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 136-137 200449 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; 卷 1992-February).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - An analog neural network processor for self-organizing mapping

AU - Sheu, Bing J.

AU - Choi, Joongho

AU - Chang, Chia Fen

PY - 1992

Y1 - 1992

N2 - The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.

AB - The building blocks of a self-organizing analog neural chip are shown. Its function is to evaluate the large number of dot products of the given input vectors and the stored weight vectors in a fully parallel format. Lateral competition is to be performed among the analog output voltages and the neural unit with the largest voltage level is to emerge as a single winner. Updating synapse weights is performed in a digital signal processor using an unsupervised learning rule. Design considerations addressed in the construction of the WTA (winner-take-all) circuit are: high resolution, fast operation, and layout compactness. The 4-MHz analog neural network processor chip, fabricated in a 2μm CMOS process, contains 25 neurons in the input layer and 64 neurons in the competitive layer. The behavior of the WTA circuit with only one winner for a lossy image data compression application is shown.

UR - http://www.scopus.com/inward/record.url?scp=84939704058&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.1992.200449

DO - 10.1109/ISSCC.1992.200449

M3 - 会议稿件

AN - SCOPUS:84939704058

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 136

EP - 137

BT - Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 39th IEEE International Solid-State Circuits Conference, ISSCC 1992

Y2 - 19 February 1992 through 21 February 1992

ER -

Sheu BJ, Choi J, Chang CF. An analog neural network processor for self-organizing mapping. 於 Digest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 136-137. 200449. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.1992.200449

An analog neural network processor for self-organizing mapping

摘要

出版系列

Conference

文獻附註

存取文件

其它文件與鏈接

指紋

引用此