An IDD receiver of LDPC coded modulation scheme for flash memory applications

A previous study shows that a low-density parity-check (LDPC) coded modulation scheme with an extremely sparse parity-check matrix and non-Gray mapping is able to achieve an error-rate performance compatible to that of a conventional Gray-mapping based scheme. This paper presents an associated iterative demodulation and decoding (IDD) receiver architecture that is targeted at flash memory applications. By adopting this extremely spare LDPC code, both the storage and the computational complexity of the decoder are lowered. The complexity of demodulator is also reduced by using the proposed simplified method. Moreover, a two-codeword scheduling approach is used so as to minimize the idles and, hence, a high throughput can be achieved. Compared to the conventional Gray-based scheme, the proposed scheme provides a similar error performance and a better hardware efficiency.