Analysis of various body bias under near-Threshold-voltage CMOS circuits

I. Chyn Wey; Jing Yi Huang

doi:10.1109/ICASI.2017.7988496

Analysis of various body bias under near-Threshold-voltage CMOS circuits

I. Chyn Wey
, Jing Yi Huang

電機工程學系(含學碩博士班及碩士在職專班)

Chang Gung Memorial Hospital
Chang Gung University

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

1 引文斯高帕斯（Scopus）

摘要

In this paper, we analyzed near-Threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.

原文	英語
主出版物標題	Proceedings of the 2017 IEEE International Conference on Applied System Innovation
主出版物子標題	Applied System Innovation for Modern Technology, ICASI 2017
編輯	Teen-Hang Meen, Artde Donald Kin-Tak Lam, Stephen D. Prior
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	606-609
頁數	4
ISBN（電子）	9781509048977
DOIs	https://doi.org/10.1109/ICASI.2017.7988496
出版狀態	已出版 - 21 07 2017
事件	2017 IEEE International Conference on Applied System Innovation, ICASI 2017 - Sapporo, 日本持續時間: 13 05 2017 → 17 05 2017

出版系列

名字	Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017

Conference

Conference	2017 IEEE International Conference on Applied System Innovation, ICASI 2017
國家/地區	日本
城市	Sapporo
期間	13/05/17 → 17/05/17

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Publisher Copyright:
© 2017 IEEE.

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引用此

Wey, I. C., & Huang, J. Y. (2017). Analysis of various body bias under near-Threshold-voltage CMOS circuits. 於 T.-H. Meen, A. D. K.-T. Lam, & S. D. Prior (編輯), Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017 (頁 606-609). 文章 7988496 (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICASI.2017.7988496

Wey, I. Chyn ; Huang, Jing Yi. / Analysis of various body bias under near-Threshold-voltage CMOS circuits. Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017. 編輯 / Teen-Hang Meen ; Artde Donald Kin-Tak Lam ; Stephen D. Prior. Institute of Electrical and Electronics Engineers Inc., 2017. 頁 606-609 (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017).

@inproceedings{2254eb19c82c42d98ad7cdf7c430a308,

title = "Analysis of various body bias under near-Threshold-voltage CMOS circuits",

abstract = "In this paper, we analyzed near-Threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.",

keywords = "Body bias, CMOS, Near-Threshold-voltage",

author = "Wey, \{I. Chyn\} and Huang, \{Jing Yi\}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE International Conference on Applied System Innovation, ICASI 2017 ; Conference date: 13-05-2017 Through 17-05-2017",

year = "2017",

month = jul,

day = "21",

doi = "10.1109/ICASI.2017.7988496",

language = "英语",

series = "Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "606--609",

editor = "Teen-Hang Meen and Lam, \{Artde Donald Kin-Tak\} and Prior, \{Stephen D.\}",

booktitle = "Proceedings of the 2017 IEEE International Conference on Applied System Innovation",

address = "美国",

}

Wey, IC & Huang, JY 2017, Analysis of various body bias under near-Threshold-voltage CMOS circuits. 於 T-H Meen, ADK-T Lam & SD Prior (編輯), Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017., 7988496, Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017, Institute of Electrical and Electronics Engineers Inc., 頁 606-609, 2017 IEEE International Conference on Applied System Innovation, ICASI 2017, Sapporo, 日本, 13/05/17. https://doi.org/10.1109/ICASI.2017.7988496

Analysis of various body bias under near-Threshold-voltage CMOS circuits. / Wey, I. Chyn; Huang, Jing Yi.
Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017. 編輯 / Teen-Hang Meen; Artde Donald Kin-Tak Lam; Stephen D. Prior. Institute of Electrical and Electronics Engineers Inc., 2017. p. 606-609 7988496 (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - Analysis of various body bias under near-Threshold-voltage CMOS circuits

AU - Wey, I. Chyn

AU - Huang, Jing Yi

PY - 2017/7/21

Y1 - 2017/7/21

N2 - In this paper, we analyzed near-Threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.

AB - In this paper, we analyzed near-Threshold-voltage (NTV) CMOS circuits with various body bias and proposed an NTV adder design with dual body bias. By adopting different body bias in the same time, adder delay and leakage power can be reduced. Also, the critical path is optimized to achieve better energy efficiency. The performance analysis are all performed under TSMC 90nm CMOS process with Monte Carlo simulation.

KW - Body bias

KW - CMOS

KW - Near-Threshold-voltage

UR - https://www.scopus.com/pages/publications/85028566354

U2 - 10.1109/ICASI.2017.7988496

DO - 10.1109/ICASI.2017.7988496

M3 - 会议稿件

AN - SCOPUS:85028566354

T3 - Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017

SP - 606

EP - 609

BT - Proceedings of the 2017 IEEE International Conference on Applied System Innovation

A2 - Meen, Teen-Hang

A2 - Lam, Artde Donald Kin-Tak

A2 - Prior, Stephen D.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE International Conference on Applied System Innovation, ICASI 2017

Y2 - 13 May 2017 through 17 May 2017

ER -

Wey IC, Huang JY. Analysis of various body bias under near-Threshold-voltage CMOS circuits. 於 Meen TH, Lam ADKT, Prior SD, 編輯, Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 606-609. 7988496. (Proceedings of the 2017 IEEE International Conference on Applied System Innovation: Applied System Innovation for Modern Technology, ICASI 2017). doi: 10.1109/ICASI.2017.7988496

Analysis of various body bias under near-Threshold-voltage CMOS circuits

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