摘要
An analytical delay model of a CMOS inverter is introduced for the first time which includes channel-length modulation, source-drain resistance and high-field effects. Calculations of the rise, fall and delay times show good agreement with SPICE simulations.
| 原文 | 英語 |
|---|---|
| 頁(從 - 到) | 408-410 |
| 頁數 | 3 |
| 期刊 | Electronics Letters |
| 卷 | 28 |
| 發行號 | 4 |
| DOIs | |
| 出版狀態 | 已出版 - 02 1992 |
| 對外發佈 | 是 |
指紋
深入研究「Analytical delay model of CMOS inverter including channel-length modulation」主題。共同形成了獨特的指紋。引用此
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