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Automated wafer defect map generation for process yield improvement

  • Nanyang Technological University

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

8 引文 斯高帕斯(Scopus)

摘要

Spatial Signature Analysis (SSA) is used to detect a reoccurring failure signature in today wafer fabrication. In order for SSA to be effective, it must correlate the signature to a wafer defect maps library. However, classifying the signatures for the library is time consuming and tedious. The Manual Visual Inspection (MVI) of several failure bins in a wafer map for multiple lots can lead to fatigue for the operator and resulted in inaccurate representation of the failure signature. Hence, an automated wafer map extraction process is proposed here to replace the MVI while ensuring accuracy of the failure signature library. Clustering tool namely Density-Based Spatial Clustering of Applications with Noise (DBSCAN) is utilized to extract the wafer spatial signature while ignoring the outliners. The appropriate size for the clustered signature is investigated and its performance is compared to the MVI signature. The analysis shows that for 3 selected failure modes, 20% occurrence rate clustered pattern provide similar performance to a 50% MVI signature. The proposed technique leads to a significant reduction in the time required for extracting current and new signatures, allowing faster yield response and improvement.

原文英語
主出版物標題2011 International Symposium on Integrated Circuits, ISIC 2011
頁面313-316
頁數4
DOIs
出版狀態已出版 - 2011
對外發佈是
事件2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore, 新加坡
持續時間: 12 12 2011 → 14 12 2011

出版系列

名字2011 International Symposium on Integrated Circuits, ISIC 2011

Conference

Conference2011 International Symposium on Integrated Circuits, ISIC 2011
國家/地區新加坡
城市SingaporeSingapore
期間12/12/11 → 14/12/11

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