BIST testability enhancement of system-level circuits: Experience with an industrial design

One major drawback of the LFSR-based BIST is its low fault coverage. To obtain the complete fault coverage, multiple seeds and multiple polynomials are usually required. One way to find the seeds and polynomials for the LFSR was utilizing the Gauss-elimination procedure. In the approach, the test patterns which are generated by LFSR are modeled as a set of multi-variable linear equations. It is created from a given deterministic test set. The corresponding seed and polynomial are then obtained from the solution of the equations set. However, given the orginal deterministic test set without don't cares, were not acceptable on the random pattern resistant circuit. In this paper, we allow the test patterns to have don't care values. With an intelligent heuristic of further utilizing the essential faults, this approach becomes much more efficient even for the random pattern resistant circuits. The experimental results on the ISCAS-85 and the ISCAS-89 benchmarks show that a significant improvement can be obtained both on the hardware overhead and the test length.