Comparison of stress-induced voiding phenomena in copper line-via structures with different dielectric materials

The package level stress-induced voiding (SIV) test of Cu dual-damascene line-via structures is performed. Two different dielectrics, undoped silica glass (USG) and carbon doped oxide (CDO), are used in this work. After 1344 h of high temperature storage test, the resistance drift of USG interconnects is found to be much smaller than that of CDO interconnects and voids are located at the bottom of the via for both USG and CDO interconnects. However, horizontal voids grown along the via bottom is observed for USG interconnects, whilst voids are found to grow vertically along the via sidewall for CDO interconnects. The phenomena are explained using finite element analysis in this work, and the observed poor SIV performance for CDO interconnects is also explained. With this finite element analysis, the implications of different low-k dielectrics on SIV reliability are discussed.