Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems

Sung Chuan Fang*, Kuo En Chang, Wu Shiung Feng, Sao Jie Chen

*此作品的通信作者

研究成果: 圖書/報告稿件的類型會議稿件同行評審

11 引文 斯高帕斯(Scopus)

摘要

A segment-crossing graph model is introduced, and a heuristic algorithm is proposed on the basis of this graph model. The algorithm is divided into two steps: Global Minimization and Local Minimization. In addition, practical considerations such as restricted terminals and adjacent limitations are addressed. The algorithm is evaluated by some routing examples using five layers. The results show that 45% of vias minimized are obtained on an average.

原文英語
主出版物標題Proceedings - Design Automation Conference
發行者Publ by IEEE
頁面60-65
頁數6
ISBN(列印)0818691492, 9780818691492
DOIs
出版狀態已出版 - 1991
事件Proceedings of the 28th ACM/IEEE Design Automation Conference - San Francisco, CA, USA
持續時間: 17 06 199121 06 1991

出版系列

名字Proceedings - Design Automation Conference
ISSN(列印)0146-7123

Conference

ConferenceProceedings of the 28th ACM/IEEE Design Automation Conference
城市San Francisco, CA, USA
期間17/06/9121/06/91

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