Cost-effective multi-standard video transform core using time-sharing architecture

Yun Hua Tseng; Yuan Ho Chen; Chih Wen Lu

doi:10.1109/ISNE.2016.7543357

Cost-effective multi-standard video transform core using time-sharing architecture

Yun Hua Tseng
, Yuan Ho Chen
, Chih Wen Lu

電子工程學系(含學碩博士班)

National Tsing Hua University

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

摘要

This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.

原文	英語
主出版物標題	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781509024391
DOIs	https://doi.org/10.1109/ISNE.2016.7543357
出版狀態	已出版 - 12 08 2016
事件	5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, 台灣持續時間: 04 05 2016 → 06 05 2016

出版系列

名字	2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Conference

Conference	5th International Symposium on Next-Generation Electronics, ISNE 2016
國家/地區	台灣
城市	Hsinchu
期間	04/05/16 → 06/05/16

文獻附註

Publisher Copyright:
© 2016 IEEE.

存取文件

10.1109/ISNE.2016.7543357

其它文件與鏈接

Link to publication in Scopus

引用此

Tseng, Y. H., Chen, Y. H., & Lu, C. W. (2016). Cost-effective multi-standard video transform core using time-sharing architecture. 於 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016 文章 7543357 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISNE.2016.7543357

@inproceedings{a793f916403f43e4a85e5de1f0d3f463,

title = "Cost-effective multi-standard video transform core using time-sharing architecture",

abstract = "This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100\%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.",

keywords = "Two-dimensional inverse discrete cosine transform (2D-IDCT), cost-efficitive, distributed arithmetic (DA), multi-standard transform, time-sharing",

author = "Tseng, \{Yun Hua\} and Chen, \{Yuan Ho\} and Lu, \{Chih Wen\}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 5th International Symposium on Next-Generation Electronics, ISNE 2016 ; Conference date: 04-05-2016 Through 06-05-2016",

year = "2016",

month = aug,

day = "12",

doi = "10.1109/ISNE.2016.7543357",

language = "英语",

series = "2016 5th International Symposium on Next-Generation Electronics, ISNE 2016",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2016 5th International Symposium on Next-Generation Electronics, ISNE 2016",

address = "美国",

}

Tseng, YH, Chen, YH & Lu, CW 2016, Cost-effective multi-standard video transform core using time-sharing architecture. 於 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016., 7543357, 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016, Institute of Electrical and Electronics Engineers Inc., 5th International Symposium on Next-Generation Electronics, ISNE 2016, Hsinchu, 台灣, 04/05/16. https://doi.org/10.1109/ISNE.2016.7543357

Cost-effective multi-standard video transform core using time-sharing architecture. / Tseng, Yun Hua; Chen, Yuan Ho; Lu, Chih Wen.
2016 5th International Symposium on Next-Generation Electronics, ISNE 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7543357 (2016 5th International Symposium on Next-Generation Electronics, ISNE 2016).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - Cost-effective multi-standard video transform core using time-sharing architecture

AU - Tseng, Yun Hua

AU - Chen, Yuan Ho

AU - Lu, Chih Wen

PY - 2016/8/12

Y1 - 2016/8/12

N2 - This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.

AB - This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.

KW - Two-dimensional inverse discrete cosine transform (2D-IDCT)

KW - cost-efficitive

KW - distributed arithmetic (DA)

KW - multi-standard transform

KW - time-sharing

UR - https://www.scopus.com/pages/publications/84985906457

U2 - 10.1109/ISNE.2016.7543357

DO - 10.1109/ISNE.2016.7543357

M3 - 会议稿件

AN - SCOPUS:84985906457

T3 - 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

BT - 2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 5th International Symposium on Next-Generation Electronics, ISNE 2016

Y2 - 4 May 2016 through 6 May 2016

ER -

Cost-effective multi-standard video transform core using time-sharing architecture

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