Degradation mechanisms in gate-all-around silicon Nanowire field effect transistor under electrostatic discharge stress a modeling approach

Cher Ming Tan*, Xiangchen Chen

*此作品的通信作者

研究成果: 期刊稿件文章同行評審

2 引文 斯高帕斯(Scopus)

摘要

The failure and degradation mechanisms of gate-all-around silicon nanowire FET subjected to electrostatic discharge (ESD) are investigated through device modeling. Transmission line pulse stress test is simulated and device degradation physics is modeled. The device degradation level, interface state concentration and hard breakdown are shown and analyzed. From the model, we found that ESD stress can induce severe performance degradation or even hard breakdown of gate-all-around nanowire device, and the interface traps due to hot carrier injection is responsible for the device degradation.

原文英語
文章編號11
期刊Nano Convergence
1
發行號1
DOIs
出版狀態已出版 - 12 2014
對外發佈

文獻附註

Publisher Copyright:
© 2014, Tan and Chen.

指紋

深入研究「Degradation mechanisms in gate-all-around silicon Nanowire field effect transistor under electrostatic discharge stress a modeling approach」主題。共同形成了獨特的指紋。

引用此