Degradation mechanisms in gate-all-around silicon Nanowire field effect transistor under electrostatic discharge stress a modeling approach

The failure and degradation mechanisms of gate-all-around silicon nanowire FET subjected to electrostatic discharge (ESD) are investigated through device modeling. Transmission line pulse stress test is simulated and device degradation physics is modeled. The device degradation level, interface state concentration and hard breakdown are shown and analyzed. From the model, we found that ESD stress can induce severe performance degradation or even hard breakdown of gate-all-around nanowire device, and the interface traps due to hot carrier injection is responsible for the device degradation.