Design and characterization of analog VLSI neural network modules

High-speed computational capabilities of artificial neural networks can be used to solve many complex pattern recognition and image processing problems in science and engineering applications. These networks are implemented in VLSI technologies as regular arrays of analog or digital circuit cells. Although neural networks inherently contain some degree of fault tolerance, a significant percentage of possible processing defects can result in failure of the network. In order to assure the quality and reliability of neural networks, a systematic method to test large arrays of analog, digital, or mixed-signal circuit components that constitute these networks is necessary. A detailed testing procedure for such networks, consisting of a parametric test and a behavioral test, is described. Characteristics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Stochastic analysis of the parametric test results can be used to predict chip yield information. Several measurement results from two analog neural network processor designs that are fabricated in 2- μ m double-polysilicon CMOS technologies are presented to demonstrate the testing procedure.