TY - GEN
T1 - Design of an asynchronous pipelined processor
AU - Chang, Meng Chou
AU - Shiau, Da Sen
PY - 2008
Y1 - 2008
N2 - Asynchronous circuits have the potential advantages of low power consumption, high operating speed, low electromagnetic emission, no clock skew problem, and robustness towards variations in temperature, supply voltage and fabrication process parameters. This paper introduces the design of an asynchronous pipelined processor, called AsynRISC, which is implemented by using the asynchronous hardware description language Balsa. Since asynchronous logic adopts distributed control scheme, the traditional methods for handling hazards in synchronous processors can not be directly applied to asynchronous processors. In this paper, the methods for dealing with data hazards and control hazards in AsynRISC are discussed.
AB - Asynchronous circuits have the potential advantages of low power consumption, high operating speed, low electromagnetic emission, no clock skew problem, and robustness towards variations in temperature, supply voltage and fabrication process parameters. This paper introduces the design of an asynchronous pipelined processor, called AsynRISC, which is implemented by using the asynchronous hardware description language Balsa. Since asynchronous logic adopts distributed control scheme, the traditional methods for handling hazards in synchronous processors can not be directly applied to asynchronous processors. In this paper, the methods for dealing with data hazards and control hazards in AsynRISC are discussed.
UR - http://www.scopus.com/inward/record.url?scp=58149146858&partnerID=8YFLogxK
U2 - 10.1109/ICCCAS.2008.4657958
DO - 10.1109/ICCCAS.2008.4657958
M3 - 会议稿件
AN - SCOPUS:58149146858
SN - 9781424420636
T3 - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
SP - 1093
EP - 1096
BT - 2008 International Conference on Communications, Circuits and Systems Proceedings, ICCCAS 2008
T2 - 2008 International Conference on Communications, Circuits and Systems, ICCCAS 2008
Y2 - 25 May 2008 through 27 May 2008
ER -