Determination of strength of Si interposers using PoEF test associated with acoustic emission method

Semiconductor companies have developed 2.5D IC integration technology, which applies a silicon interposer with Cu through silicon vias (Cu TSVs) as a platform for interconnecting and integrating heterogeneous chips horizontally and vertically as a transition approach to 3D IC. The existing Cu TSVs might make the silicon interposers more fragile, due to structural non-homogeneity and weak interface. Thus, the strength determination of silicon interposers becomes one of important issues for ensuring reliability of 2.5D packages. The purpose of this study is to determine the strength of silicon interposers using a point-load-on-elastic-foundation (PoEF) test, associated with an acoustic emission (AE) method of detecting local material cracks or delamination occurring during the test before the interposer breaking. The results indicate that there are some less-than-50 dB AE signals occurring before the interposer breaking, due to the micropad crush induced by the loading-pin contact. However, the interposer breaking is found to be controlled by the maximum tensile stresses located at the corner of C4 bump pad, instead of micropad crush or Cu TSV. This failure behavior has been validated by finite element simulation and further the strength of silicon interposer has been successfully determined by experimental data associated with a finite element analysis by taking into account Cu material nonlinear properties.