摘要
The purpose of this paper is to design and measure an H-plane substrate integrated waveguide (SIW) 72 GHz backfired horn antenna chip. The SIW horn was fabricated on a standard 0.5-μm GaAs process with substrate thickness of 100 μm. Planar SIW horn design method with standard GaAs circuit design rule was adopted. The input reflection coefficient and output antenna gain was simulated at the FEM-based 3D full-wave EM solver, Ansoft HFSS and measured at the Agilent E8361C Network Analyzer and Cascade 110 GHz probe station. The measured input −6 dB bandwidth is about 0.9 GHz at a center frequency of 72.39 GHz. The maximum antenna power gain extracted from the path loss at 72.39 GHz is about −3.64 dBi. Thin substrate exhibits larger capacitance and energy stores rather than radiates. Flat cutting restricts the arc lens design and results in the radiation plane mismatches to the air. Simple taper transition design makes the input bandwidth much narrower. The problems can be further improved by selecting thicker substrate and the multi-section input CPW GSG pads to microstrip transition. Unlike the traditional anechoic chamber, the antenna measurement station is exposed to the open space and chip antenna was supported by the FR4 substrate and the metal probing station plate. A fully characterization of the antenna open space environment before the measurement is needed. An H-plane SIW 72 GHz horn antenna was designed and studied. The antenna was using the GaAs 0.5-μm MMICs process design rule includes the SIW designed cylindrical metal bars all being restricted in standard rectangular shape. Compare to traditional bulky waveguide horn antenna, the antenna chip size is only 1.8×1.7 mm2. The on-wafer measurement is conducted to measure the input return loss and the maximum antenna power gain of the on-chip antenna. The designed on-chip SIW horn antenna is useful for the integrated design of the E band GaAs MMICs single-chip RF transceiver.
原文 | 英語 |
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頁(從 - 到) | 431-441 |
頁數 | 11 |
期刊 | COMPEL - The international journal for computation and mathematics in electrical and electronic engineering |
卷 | 32 |
發行號 | 2 |
DOIs | |
出版狀態 | 已出版 - 01 03 2013 |