Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr203/SiOxN y gate dielectric

Tune Ming Pan; Tin Wei Wu; Ching Lin Chan; Kai Ming Chen; Chih Hong Lee

doi:10.1149/1.2911494

Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric

Tune Ming Pan^*
, Tin Wei Wu
, Ching Lin Chan
, Kai Ming Chen
, Chih Hong Lee

^*此作品的通信作者

Chang Gung University

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

摘要

In this paper, we have developed a stacked Pr₂O ₃/SiO_xN_y gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high I_on/I_off current ratio. This phenomenon is attributed to the smooth Pr₂O₃/poly-Si interface and the low interface trap density provided by N₂O plasma treatment. The presence of an SiO_xN_y buffer layer also enhanced the electrical reliability of the Pr₂O₃/poly-Si TFT. All of these results suggest that a high-k Pr₂O₃ gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

原文	英語
主出版物標題	ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4
主出版物子標題	New Materials, Processes, and Equipment
頁面	151-155
頁數	5
版本	1
DOIs	https://doi.org/10.1149/1.2911494
出版狀態	已出版 - 2008
事件	Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4 - Phoenix, AZ, 美國持續時間: 18 05 2008 → 22 05 2008

出版系列

名字	ECS Transactions
號碼	1
卷	13
ISSN（列印）	1938-5862
ISSN（電子）	1938-6737

Conference

Conference	Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4
國家/地區	美國
城市	Phoenix, AZ
期間	18/05/08 → 22/05/08

存取文件

10.1149/1.2911494

其它文件與鏈接

Link to publication in Scopus

引用此

Pan, T. M., Wu, T. W., Chan, C. L., Chen, K. M., & Lee, C. H. (2008). Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. 於 ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment (1 編輯, 頁 151-155). (ECS Transactions; 卷 13, 編號 1). https://doi.org/10.1149/1.2911494

Pan, Tune Ming ; Wu, Tin Wei ; Chan, Ching Lin 等. / Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1. 編輯 2008. 頁 151-155 (ECS Transactions; 1).

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title = "Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr203/SiOxN y gate dielectric",

abstract = "In this paper, we have developed a stacked Pr2O 3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high Ion/Ioff current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.",

author = "Pan, \{Tune Ming\} and Wu, \{Tin Wei\} and Chan, \{Ching Lin\} and Chen, \{Kai Ming\} and Lee, \{Chih Hong\}",

year = "2008",

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Pan, TM, Wu, TW, Chan, CL, Chen, KM & Lee, CH 2008, Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. 於 ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1 edn, ECS Transactions, 編號 1, 卷 13, 頁 151-155, Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, 4, Phoenix, AZ, 美國, 18/05/08. https://doi.org/10.1149/1.2911494

Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. / Pan, Tune Ming; Wu, Tin Wei; Chan, Ching Lin 等.
ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1. 編輯 2008. p. 151-155 (ECS Transactions; 卷 13, 編號 1).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

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AU - Chen, Kai Ming

AU - Lee, Chih Hong

PY - 2008

Y1 - 2008

N2 - In this paper, we have developed a stacked Pr2O 3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high Ion/Ioff current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

AB - In this paper, we have developed a stacked Pr2O 3/SiOxNy gate dielectric into low-temperature poly-Si thin-film transistors (TFTs). High-performance TFT devices can be achieved including a high effective carrier mobility, high driving current, small subthreshold swing, and high Ion/Ioff current ratio. This phenomenon is attributed to the smooth Pr2O3/poly-Si interface and the low interface trap density provided by N2O plasma treatment. The presence of an SiOxNy buffer layer also enhanced the electrical reliability of the Pr2O3/poly-Si TFT. All of these results suggest that a high-k Pr2O3 gate dielectric prepared the buffer layer is a good candidate for high-performance TFTs.

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Pan TM, Wu TW, Chan CL, Chen KM, Lee CH. Electrical characteristics of low-temperature poly-silicon thin-film transistor using a stacked Pr₂0₃/SiO_xN _y gate dielectric. 於 ECS Transactions - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment. 1 編輯 2008. p. 151-155. (ECS Transactions; 1). doi: 10.1149/1.2911494