摘要
The purpose of this study is to evaluate the strength of TSV silicon chips using a point-load on elastic foundation (PoEF) test, associated with an acoustic emission (AE) method for detecting local material cracks or delamination occurring during the test before the chip breaking (or catastrophic failure). The results indicate that there are no larger-than-25 dB AE signals and no via cracks occurring before the chip breaking. However, the delamination between copper cap and silicon dioxide surface (due to poor adhesion), and bond pad crash on loading contact were found occurring with 50 dB of AE signals, respectively. It has been concluded that the strength of TSV chip is governed by the via interfacial crack failure occurring right at the maximum load.
| 原文 | 英語 |
|---|---|
| 主出版物標題 | 2016 International Conference on Electronics Packaging, ICEP 2016 |
| 發行者 | Institute of Electrical and Electronics Engineers Inc. |
| 頁面 | 294-297 |
| 頁數 | 4 |
| ISBN(電子) | 9784904090176 |
| DOIs | |
| 出版狀態 | 已出版 - 07 06 2016 |
| 事件 | 2016 International Conference on Electronics Packaging, ICEP 2016 - Hokkaido, 日本 持續時間: 20 04 2016 → 22 04 2016 |
出版系列
| 名字 | 2016 International Conference on Electronics Packaging, ICEP 2016 |
|---|
Conference
| Conference | 2016 International Conference on Electronics Packaging, ICEP 2016 |
|---|---|
| 國家/地區 | 日本 |
| 城市 | Hokkaido |
| 期間 | 20/04/16 → 22/04/16 |
文獻附註
Publisher Copyright:© 2016 The Japan Institute of Electronics Packaging.
指紋
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