摘要
For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.
原文 | 英語 |
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主出版物標題 | 2019 IEEE International Electron Devices Meeting, IEDM 2019 |
發行者 | Institute of Electrical and Electronics Engineers Inc. |
ISBN(電子) | 9781728140315 |
DOIs | |
出版狀態 | 已出版 - 12 2019 |
對外發佈 | 是 |
事件 | 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, 美國 持續時間: 07 12 2019 → 11 12 2019 |
出版系列
名字 | Technical Digest - International Electron Devices Meeting, IEDM |
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卷 | 2019-December |
ISSN(列印) | 0163-1918 |
Conference
Conference | 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 |
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國家/地區 | 美國 |
城市 | San Francisco |
期間 | 07/12/19 → 11/12/19 |
文獻附註
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