High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics

Tung Ming Pan*, Chih Jen Chang

*此作品的通信作者

研究成果: 期刊稿件文章同行評審

18 引文 斯高帕斯(Scopus)

摘要

In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm 2 V-1 s-1, small subthreshold slope of 269 mV dec-1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O 3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.

原文英語
文章編號075004
期刊Semiconductor Science and Technology
26
發行號7
DOIs
出版狀態已出版 - 07 07 2011

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