TY - JOUR
T1 - High-performance poly-silicon TFTs with high-k Y2O3 gate dielectrics
AU - Pan, Tung Ming
AU - Chang, Chih Jen
PY - 2011/7/7
Y1 - 2011/7/7
N2 - In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm 2 V-1 s-1, small subthreshold slope of 269 mV dec-1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O 3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.
AB - In this paper, we describe a poly-Si thin-film transistor (TFT) incorporating a high-k Y2O3 gate dielectric for different annealing times. The high-k Y2O3 poly-Si TFT device annealed in O2 gas for 60 min exhibited better electrical characteristics in terms of a high effective carrier mobility of 32.7 cm 2 V-1 s-1, small subthreshold slope of 269 mV dec-1, and high Ion/Ioff current ratio of 1.83 × 107. This result is attributed to a smooth surface, structural relaxation, and a low trap-state density at the Y2O 3/poly-Si interface after a long time thermal annealing. All of these results suggest that the 60 min annealed poly-Si Y2O3 TFT is a good candidate for high-performance low-temperature poly-Si TFTs.
UR - http://www.scopus.com/inward/record.url?scp=79953837368&partnerID=8YFLogxK
U2 - 10.1088/0268-1242/26/7/075004
DO - 10.1088/0268-1242/26/7/075004
M3 - 文章
AN - SCOPUS:79953837368
SN - 0268-1242
VL - 26
JO - Semiconductor Science and Technology
JF - Semiconductor Science and Technology
IS - 7
M1 - 075004
ER -