TY - GEN
T1 - High performance V-band GaAs power amplifier and low noise amplifier using low-loss transmission line technology
AU - Chiu, Hsien Chin
AU - Ke, Bo Yu
PY - 2012
Y1 - 2012
N2 - We present the design and measurement results of millimeter-wave integrated circuits implemented in 0.15-m baseline GaAs pHEMT. Both active and passive test structures were measured. We present the design of an on-chip slow wave transmission line and RF amplifier from low loss with low noise parameter measurement results at V-band. Finally, the design and measurement result of two amplifiers for low noise amplifier (LNA) and power amplifier (PA). The three-stage LNA matching networks and RF-chock were based upon slow wave transmissions lines (TLs). Peak gain of 13.2 dB at 66 GHz, in-band minimum noise figure less then 5 dB under 3-V supply voltage were obtained at a power consumption of 89 mW. The two stage power amplifier with push-pull combination in balun structure achieves a peak gain of 16.8 dB at 58 GHz OP1dB of 11.5 dBm, Psat of 16.7 dBm, and PAE of 19.8% under 3-V supply voltage were obtained at a power consumption of 188 mW. The chip size, the LNA and PA die area including all Pads are 1.250.6 and 1.34 0.6 mm 2, respectively. The LNA and PA MMICs demonstrate the superior gain and power performance in low-loss TLs technology.
AB - We present the design and measurement results of millimeter-wave integrated circuits implemented in 0.15-m baseline GaAs pHEMT. Both active and passive test structures were measured. We present the design of an on-chip slow wave transmission line and RF amplifier from low loss with low noise parameter measurement results at V-band. Finally, the design and measurement result of two amplifiers for low noise amplifier (LNA) and power amplifier (PA). The three-stage LNA matching networks and RF-chock were based upon slow wave transmissions lines (TLs). Peak gain of 13.2 dB at 66 GHz, in-band minimum noise figure less then 5 dB under 3-V supply voltage were obtained at a power consumption of 89 mW. The two stage power amplifier with push-pull combination in balun structure achieves a peak gain of 16.8 dB at 58 GHz OP1dB of 11.5 dBm, Psat of 16.7 dBm, and PAE of 19.8% under 3-V supply voltage were obtained at a power consumption of 188 mW. The chip size, the LNA and PA die area including all Pads are 1.250.6 and 1.34 0.6 mm 2, respectively. The LNA and PA MMICs demonstrate the superior gain and power performance in low-loss TLs technology.
UR - http://www.scopus.com/inward/record.url?scp=84864035433&partnerID=8YFLogxK
U2 - 10.1109/HSIC.2012.6212968
DO - 10.1109/HSIC.2012.6212968
M3 - 会议稿件
AN - SCOPUS:84864035433
SN - 9781467306751
T3 - 2012 4th International High Speed Intelligent Communication Forum, HSIC 2012, Proceeding
SP - 205
EP - 208
BT - 2012 4th International High Speed Intelligent Communication Forum, HSIC 2012, Proceeding
T2 - 2012 4th International High Speed Intelligent Communication Forum, HSIC 2012
Y2 - 10 May 2012 through 11 May 2012
ER -