High-speed bit-parallel systolic multipliers for a class of GF(2m)

C. Y. Lee*, E. H. Lu, Jau-Yien

*此作品的通信作者

研究成果: 會議稿件的類型論文同行評審

3 引文 斯高帕斯(Scopus)

摘要

Two special operations, called the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplication over a class of GF(2m) was developed in this paper. The low-complexity bit-parallel systolic multipliers are presented. The multiplier is composed of (m+1)2 identical cells, each of which consisting of one 2-bit AND gate, one 2-bit XOR gate and three 1-bit latches. The multiplier has very low latency and propagation delay, which makes them very fast. Moreover the architectures of the multiplier can also be applied to compute multiplication over the class of GF(2nr) in which the elements are represented with the root of an irreducible equally spaced polynomial of degree nr.

原文英語
頁面291-294
頁數4
出版狀態已出版 - 2001
事件2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, 台灣
持續時間: 18 04 200120 04 2001

Conference

Conference2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
國家/地區台灣
城市Hsinchu
期間18/04/0120/04/01

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