High-speed charge transfer sense amplifier for 0.5 v DRAM array applications

A new high-speed charge transfer sense amplifier scheme is proposed for 0.5V DRAM array applications. The combination of both the cross-coupled structure and the boosting capacitance used in the proposed sense amplifier leads to a maximum voltage difference between sense nodes. Based on post-layout simulations, the charge transfer speed and the voltage difference after charge transfer are improved 40.7% and 59.29%, respectively, over the prior art circuits. The power-delay product is then enhanced 38.26%. Besides, both high voltage pre-charge levels and high voltage control signals are not required in this proposed circuit as compared with prior arts.