Improvement in junction breakdown and GIDL using MFLA in DRAM product

In this study, we successfully improved junction breakdown using millisecond flash anneal (MFLA) on a dynamic random access memory (DRAM) product. By replacing a rapid thermal annealing (RTA) process with MFLA after contact implantation, improvements in NMOS and PMOS junctions were observed and no degradation was found. Device simulation data show that the PMOS junction electric field (E-field) was reduced with MFLA and that MFLA has an advantage in junction profile tailoring. The behavior of gate-induced drain leakage (GIDL) at different process stages with different annealing temperatures was studied. The preheat and peak temperatures of MFLA were found to be correlated with GIDL improvement. The optimum condition in this study was 1200C flash anneal with a 750C preheat temperature. Bright field and weak-beam dark-field transmission electron microscopy images showed perfect dislocation loops and fault dislocation loops remaining in the {113} plane with a size of around 17 20 nm in the junction area.