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Integrated All-GaN Driver for High-voltage DC-DC Power Converters

  • Chang Gung University

研究成果: 圖書/報告稿件的類型會議稿件同行評審

1 引文 斯高帕斯(Scopus)

摘要

This article presents a high-voltage power converter based on an all-GaN half-bridge architecture, incorporating a novel pulse-charging bootstrap circuit. The proposed half-bridge using only E-mode and D-mode GaN transistors integrates the power switches and drivers on the same substrate to suppress parasitic effects and output ringing, thereby improving the overall performance of the converter. The high-side gate driver adopts the E-stacked/D/E-mode (EDE) architecture to directly drive the power transistor's gate with a low-voltage signal, without additional level shifters, simplifying design and reducing propagation delay. Moreover, the architecture exploits GaN's reverse-conducting property as an active diode to charge the bootstrap capacitor, mitigating excessive DC losses and improving overall efficiency. The low-side power transistor is driven by a stack of two D/E-mode devices, with a minimum gate drive voltage of -5 V, preventing false triggering when the low-side driver is turned off. The proposed fully integrated half-bridge is implemented in a 0.5 μm GaN process and simulated in Cadence Spectre in a buck power converter. For an input voltage above 400V, the half-bridge outputs a driving voltage with an operating frequency greater than 1 MHz and generates pulse waves with a rise time and fall time of 50.4 nsec and 52.6 nsec, respectively.

原文英語
主出版物標題Proceedings - International SoC Design Conference 2023, ISOCC 2023
發行者Institute of Electrical and Electronics Engineers Inc.
頁面175-176
頁數2
ISBN(電子)9798350327038
DOIs
出版狀態已出版 - 2023
事件20th International SoC Design Conference, ISOCC 2023 - Jeju, 韓國
持續時間: 25 10 202328 10 2023

出版系列

名字Proceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference20th International SoC Design Conference, ISOCC 2023
國家/地區韓國
城市Jeju
期間25/10/2328/10/23

文獻附註

Publisher Copyright:
© 2023 IEEE.

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