Integrated FPGA based ASIC design on error code correction counter for UPS telecommunication

The paper presents a hybrid error code correction counter suitable for the UPS telecommunication with three different signal specifications. Based on the FPGA implementation, the required functional blocks can be partitioned and designed as follows: pulse combination, serial to parallel data transfer, one frame latching, combination logic to serial pulse generation, MPU based one second pulse generation, asynchronous counter with asynchronous clear. Through systematic integration as described in this paper, the error code correction counter can be successfully designed. It is believed that the associated implementation technique will be applicable to the research and development of the tester technology on the UPS telecommunication.