Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

X. R. Yu; M. H. Chuang; S. W. Chang; W. H. Chang; T. C. Hong; C. H. Chiang; W. H. Lu; C. Y. Yang; W. J. Chen; J. H. Lin; P. H. Wu; T. C. Sun; S. Kola; Y. S. Yang; Yun Da; P. J. Sung; C. T. Wu; T. C. Cho; G. L. Luo; K. H. Kao; M. H. Chiang; W. C.Y. Ma; C. J. Su; T. S. Chao; T. Maeda; S. Samukawa; Y. Li; Y. J. Lee; W. F. Wu; J. H. Tarng; Y. H. Wang

doi:10.1109/IEDM45625.2022.10019507

Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

X. R. Yu^*
, M. H. Chuang
, S. W. Chang
, W. H. Chang
, T. C. Hong
, C. H. Chiang
, W. H. Lu
, C. Y. Yang
, W. J. Chen
, J. H. Lin
, P. H. Wu
, T. C. Sun
, S. Kola
, Y. S. Yang
, Yun Da
, P. J. Sung
, C. T. Wu
, T. C. Cho
, G. L. Luo
, K. H. Kao

M. H. Chiang, W. C.Y. Ma, C. J. Su, T. S. Chao, T. Maeda, S. Samukawa, Y. Li, Y. J. Lee, W. F. Wu, J. H. Tarng, Y. H. Wang

^*此作品的通信作者

National Cheng Kung University
National Yang Ming Chiao Tung University
Taiwan Semiconductor Research Institute (TSRI)
National Institute of Advanced Industrial Science and Technology
National Sun Yat-sen University
National University of Kaohsiung

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

21 引文斯高帕斯（Scopus）

摘要

In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42% area reduction.

原文	英語
主出版物標題	2022 International Electron Devices Meeting, IEDM 2022
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	2051-2054
頁數	4
ISBN（電子）	9781665489591
DOIs	https://doi.org/10.1109/IEDM45625.2022.10019507
出版狀態	已出版 - 2022
對外發佈	是
事件	2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, 美國持續時間: 03 12 2022 → 07 12 2022

出版系列

名字	Technical Digest - International Electron Devices Meeting, IEDM
卷	2022-December
ISSN（列印）	0163-1918

Conference

Conference	2022 International Electron Devices Meeting, IEDM 2022
國家/地區	美國
城市	San Francisco
期間	03/12/22 → 07/12/22

文獻附註

Publisher Copyright:
© 2022 IEEE.

存取文件

10.1109/IEDM45625.2022.10019507

其它文件與鏈接

Link to publication in Scopus

引用此

Yu, X. R., Chuang, M. H., Chang, S. W., Chang, W. H., Hong, T. C., Chiang, C. H., Lu, W. H., Yang, C. Y., Chen, W. J., Lin, J. H., Wu, P. H., Sun, T. C., Kola, S., Yang, Y. S., Da, Y., Sung, P. J., Wu, C. T., Cho, T. C., Luo, G. L., ... Wang, Y. H. (2022). Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size. 於 2022 International Electron Devices Meeting, IEDM 2022 (頁 2051-2054). (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2022-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45625.2022.10019507

Yu, X. R. ; Chuang, M. H. ; Chang, S. W. 等. / Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size. 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., 2022. 頁 2051-2054 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{ca3b00959ed14624a30ba5e080fa7ce5,

title = "Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42\% Reduced Cell Size",

abstract = "In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42\% area reduction.",

author = "Yu, \{X. R.\} and Chuang, \{M. H.\} and Chang, \{S. W.\} and Chang, \{W. H.\} and Hong, \{T. C.\} and Chiang, \{C. H.\} and Lu, \{W. H.\} and Yang, \{C. Y.\} and Chen, \{W. J.\} and Lin, \{J. H.\} and Wu, \{P. H.\} and Sun, \{T. C.\} and S. Kola and Yang, \{Y. S.\} and Yun Da and Sung, \{P. J.\} and Wu, \{C. T.\} and Cho, \{T. C.\} and Luo, \{G. L.\} and Kao, \{K. H.\} and Chiang, \{M. H.\} and Ma, \{W. C.Y.\} and Su, \{C. J.\} and Chao, \{T. S.\} and T. Maeda and S. Samukawa and Y. Li and Lee, \{Y. J.\} and Wu, \{W. F.\} and Tarng, \{J. H.\} and Wang, \{Y. H.\}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Electron Devices Meeting, IEDM 2022 ; Conference date: 03-12-2022 Through 07-12-2022",

year = "2022",

doi = "10.1109/IEDM45625.2022.10019507",

language = "英语",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "2051--2054",

booktitle = "2022 International Electron Devices Meeting, IEDM 2022",

address = "美国",

}

Yu, XR, Chuang, MH, Chang, SW, Chang, WH, Hong, TC, Chiang, CH, Lu, WH, Yang, CY, Chen, WJ, Lin, JH, Wu, PH, Sun, TC, Kola, S, Yang, YS, Da, Y, Sung, PJ, Wu, CT, Cho, TC, Luo, GL, Kao, KH, Chiang, MH, Ma, WCY, Su, CJ, Chao, TS, Maeda, T, Samukawa, S, Li, Y, Lee, YJ, Wu, WF, Tarng, JH & Wang, YH 2022, Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size. 於 2022 International Electron Devices Meeting, IEDM 2022. Technical Digest - International Electron Devices Meeting, IEDM, 卷 2022-December, Institute of Electrical and Electronics Engineers Inc., 頁 2051-2054, 2022 International Electron Devices Meeting, IEDM 2022, San Francisco, 美國, 03/12/22. https://doi.org/10.1109/IEDM45625.2022.10019507

Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size. / Yu, X. R.; Chuang, M. H.; Chang, S. W. 等.
2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 2051-2054 (Technical Digest - International Electron Devices Meeting, IEDM; 卷 2022-December).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

AU - Yu, X. R.

AU - Chuang, M. H.

AU - Chang, S. W.

AU - Chang, W. H.

AU - Hong, T. C.

AU - Chiang, C. H.

AU - Lu, W. H.

AU - Yang, C. Y.

AU - Chen, W. J.

AU - Lin, J. H.

AU - Wu, P. H.

AU - Sun, T. C.

AU - Kola, S.

AU - Yang, Y. S.

AU - Da, Yun

AU - Sung, P. J.

AU - Wu, C. T.

AU - Cho, T. C.

AU - Luo, G. L.

AU - Kao, K. H.

AU - Chiang, M. H.

AU - Ma, W. C.Y.

AU - Su, C. J.

AU - Chao, T. S.

AU - Maeda, T.

AU - Samukawa, S.

AU - Li, Y.

AU - Lee, Y. J.

AU - Wu, W. F.

AU - Tarng, J. H.

AU - Wang, Y. H.

PY - 2022

Y1 - 2022

N2 - In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42% area reduction.

AB - In this work, we propose an advanced 3-D heterogeneous 6T SRAM with a newly designed hetero-integration method. CFET inverters and IGZO pass gates are vertically stacked within a 2T footprint area. The Low-Temperature Hetero-Layers Bonding Technique (LT-HBT) process is utilized successfully to fabricate single crystalline heterogeneous Double Layer Transferred (DLT) Ge/2Si CFET-OI on an 8-inch full wafer. Furthermore, an IGZO nFET is deposited and treated as a pass gate (PG) to realize a 6T SRAM operation. The hetero-integration of IGZO PG and self-align DLT Ge/2Si CFET inverters showed improved Read Static Noise Margin (RSNM) and stand-by leakage power. The state-of-the-art 3-D heterogeneous 6T SRAM leads to 42% area reduction.

UR - https://www.scopus.com/pages/publications/85147533584

U2 - 10.1109/IEDM45625.2022.10019507

DO - 10.1109/IEDM45625.2022.10019507

M3 - 会议稿件

AN - SCOPUS:85147533584

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 2051

EP - 2054

BT - 2022 International Electron Devices Meeting, IEDM 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 International Electron Devices Meeting, IEDM 2022

Y2 - 3 December 2022 through 7 December 2022

ER -

Yu XR, Chuang MH, Chang SW, Chang WH, Hong TC, Chiang CH 等. Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size. 於 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 2051-2054. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45625.2022.10019507

Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

摘要

出版系列

Conference

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