Investigation of Noise-Margin-Enhanced and Low-Power Memory Techniques for SoC Applications

Cihun Siyong Alex Gong*

*此作品的通信作者

研究成果: 期刊稿件文章同行評審

1 引文 斯高帕斯(Scopus)

摘要

A new memory design with a simple six-transistor memory cell achieves an enhanced read static noise margin. Based on using “pre-equalize” rather than “pre-charge” at the beginning of a read operation, the cross-coupled inverters of the memory cell have a switching threshold close to that of the conventional CMOS inverter circuit, thus achieving both compactness and increased data stability. The proposed can also potentially dramatically decrease power dissipation in conventional memory counterparts. Both simulations and measurements were carried out as proof of concept. The proposed memory hardware techniques are simple to implement and highly practical, making it quite competitive with other currently used methods.

原文英語
頁(從 - 到)1115-1128
頁數14
期刊Circuits, Systems, and Signal Processing
34
發行號4
DOIs
出版狀態已出版 - 04 2015

文獻附註

Publisher Copyright:
© 2014, Springer Science+Business Media New York.

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