Low-complexity systolic multiplier over GF(2m) using weakly dual basis

Chiou Yng Lee; Ya Cheng Lu; Erl Huei Lu

doi:10.1109/APCCAS.2002.1114972

Low-complexity systolic multiplier over GF(2^m) using weakly dual basis

Chiou Yng Lee, Ya Cheng Lu, Erl Huei Lu

電機工程學系(含學碩博士班及碩士在職專班)

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

2 引文斯高帕斯（Scopus）

摘要

This paper offers a new bit-parallel systolic multiplier for GF(2^m) using the weakly dual basis. The multiplier is composed of two units - multiplication and transformation. The structure of the multiplication unit includes m² cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log₂m] clock cycles.

原文	英語
主出版物標題	Proceedings - APCCAS 2002
主出版物子標題	Asia-Pacific Conference on Circuits and Systems
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	367-372
頁數	6
ISBN（電子）	0780376900
DOIs	https://doi.org/10.1109/APCCAS.2002.1114972
出版狀態	已出版 - 2002
事件	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, 印度尼西亞持續時間: 28 10 2002 → 31 10 2002

出版系列

名字	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
卷	1

Conference

Conference	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
國家/地區	印度尼西亞
城市	Denpasar, Bali
期間	28/10/02 → 31/10/02

文獻附註

Publisher Copyright:
© 2002 IEEE.

存取文件

10.1109/APCCAS.2002.1114972

其它文件與鏈接

Link to publication in Scopus

引用此

Lee, C. Y., Lu, Y. C., & Lu, E. H. (2002). Low-complexity systolic multiplier over GF(2^m) using weakly dual basis. 於 Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (頁 367-372). 文章 1114972 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 卷 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1114972

@inproceedings{0c3a8305f2cb4055be836a77e00d072d,

title = "Low-complexity systolic multiplier over GF(2m) using weakly dual basis",

abstract = "This paper offers a new bit-parallel systolic multiplier for GF(2m) using the weakly dual basis. The multiplier is composed of two units - multiplication and transformation. The structure of the multiplication unit includes m2 cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log2m] clock cycles.",

keywords = "Arithmetic, Circuits, Clocks, Computer architecture, Concurrent computing, Cryptography, Delay, Error correction codes, Galois fields, Polynomials",

author = "Lee, {Chiou Yng} and Lu, {Ya Cheng} and Lu, {Erl Huei}",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 ; Conference date: 28-10-2002 Through 31-10-2002",

year = "2002",

doi = "10.1109/APCCAS.2002.1114972",

language = "英语",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "367--372",

booktitle = "Proceedings - APCCAS 2002",

address = "美国",

}

Lee, CY, Lu, YC & Lu, EH 2002, Low-complexity systolic multiplier over GF(2^m) using weakly dual basis. 於 Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems., 1114972, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, 卷 1, Institute of Electrical and Electronics Engineers Inc., 頁 367-372, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, 印度尼西亞, 28/10/02. https://doi.org/10.1109/APCCAS.2002.1114972

Low-complexity systolic multiplier over GF(2^m) using weakly dual basis. / Lee, Chiou Yng; Lu, Ya Cheng; Lu, Erl Huei.
Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2002. p. 367-372 1114972 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; 卷 1).

研究成果: 圖書/報告稿件的類型 › 會議稿件 › 同行評審

TY - GEN

T1 - Low-complexity systolic multiplier over GF(2m) using weakly dual basis

AU - Lee, Chiou Yng

AU - Lu, Ya Cheng

AU - Lu, Erl Huei

PY - 2002

Y1 - 2002

N2 - This paper offers a new bit-parallel systolic multiplier for GF(2m) using the weakly dual basis. The multiplier is composed of two units - multiplication and transformation. The structure of the multiplication unit includes m2 cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log2m] clock cycles.

AB - This paper offers a new bit-parallel systolic multiplier for GF(2m) using the weakly dual basis. The multiplier is composed of two units - multiplication and transformation. The structure of the multiplication unit includes m2 cells, each cell is composed of one 2-input AND gate, one 2-input XOR gate and three/four 1-bit latches. The structure of the transformation unit is established by the 2-input XOR-tree. The latency of the multiplier only requires m+[log2m] clock cycles.

KW - Arithmetic

KW - Circuits

KW - Clocks

KW - Computer architecture

KW - Concurrent computing

KW - Cryptography

KW - Delay

KW - Error correction codes

KW - Galois fields

KW - Polynomials

UR - http://www.scopus.com/inward/record.url?scp=33745180898&partnerID=8YFLogxK

U2 - 10.1109/APCCAS.2002.1114972

DO - 10.1109/APCCAS.2002.1114972

M3 - 会议稿件

AN - SCOPUS:33745180898

T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

SP - 367

EP - 372

BT - Proceedings - APCCAS 2002

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - Asia-Pacific Conference on Circuits and Systems, APCCAS 2002

Y2 - 28 October 2002 through 31 October 2002

ER -